公开(公告)号：US11334429B2

公开(公告)日：2022-05-17

申请号：US16985241

申请日：2020-08-05

Applicant: VIA Technologies, Inc.

Inventor： Yi-Lin Lai ,  Chen-Te Chen ,  Ying-Che Chung

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  H03M13/09 ,  H03M13/15 ,  H03M13/11

Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.

公开(公告)号：US10783032B2

公开(公告)日：2020-09-22

申请号：US15662254

申请日：2017-07-27

Applicant: VIA Technologies, Inc.

Inventor： Yi-Lin Lai ,  Chen-Te Chen ,  Ying-Che Chung

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  H03M13/09 ,  H03M13/15 ,  H03M13/11

Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.

公开(公告)号：US20180329776A1

公开(公告)日：2018-11-15

申请号：US15662254

申请日：2017-07-27

Applicant: VIA Technologies, Inc.

Inventor： Yi-Lin Lai ,  Chen-Te Chen ,  Ying-Che Chung

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

CPC classification number: G06F11/1068 ,  G06F11/1004 ,  G06F11/1048 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/152 ,  H03M13/2906

Abstract: A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.