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公开(公告)号：US07234034B2
公开(公告)日：2007-06-19
申请号：US10663597
申请日：2003-09-16
IPC分类号： G06F13/00
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/22
摘要： A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
摘要翻译： 自定时存储器件包括存储器阵列，存储器输入电路和存储器控制电路。 存储器输入电路可操作以接收输入时钟信号并响应于此产生存储器操作启动信号，而存储器控制电路可操作以接收存储器操作启动信号并产生一个或多个控制信号以启动存储器操作 回应。 存储器控制电路还可操作以识别存储器操作的完成并响应于此产生周期就绪选通信号。 存储器输入电路接收周期就绪选通信号作为输入，并且响应于此产生下一个存储器操作启动信号以启动下一个存储器操作。
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2.发明授权Method of operating a memory at high speed using a cycle ready status output signal 有权使用循环就绪状态输出信号高速运行存储器的方法公开(公告)号：US07200730B2
公开(公告)日：2007-04-03
申请号：US10663144
申请日：2003-09-16
IPC分类号： G06F13/00
CPC分类号： G11C7/1063 , G11C7/04 , G11C7/1051 , G11C7/22
摘要： A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
摘要翻译： 自定时存储器件包括存储器阵列，存储器输入电路和存储器控制电路。 存储器输入电路可操作以接收输入时钟信号并响应于此产生存储器操作启动信号，而存储器控制电路可操作以接收存储器操作启动信号并产生一个或多个控制信号以启动存储器操作 回应。 存储器控制电路还可操作以识别存储器操作的完成并响应于此产生周期就绪选通信号。 存储器输入电路接收周期就绪选通信号作为输入，并且响应于此产生下一个存储器操作启动信号以启动下一个存储器操作。
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公开(公告)号：US06956789B2
公开(公告)日：2005-10-18
申请号：US10663575
申请日：2003-09-16
CPC分类号： G11C7/1063 , G11C7/1051 , G11C7/22 , G11C7/222 , G11C2207/2281
摘要： A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.
摘要翻译： 自定时存储器件包括存储器阵列，存储器输入电路和存储器控制电路。 存储器输入电路可操作以接收输入时钟信号并响应于此产生存储器操作启动信号，而存储器控制电路可操作以接收存储器操作启动信号并产生一个或多个控制信号以启动存储器操作 回应。 存储器控制电路还可操作以识别存储器操作的完成并响应于此产生周期就绪选通信号。 存储器输入电路接收周期就绪选通信号作为输入，并且响应于此产生下一个存储器操作启动信号以启动下一个存储器操作。
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4.发明授权
公开(公告)号：US6088288A
公开(公告)日：2000-07-11
申请号：US405480
申请日：1999-09-24
CPC分类号： G11C5/14 , G11C7/1078
摘要： A method of reducing power supply current transients in a memory array caused by a simultaneous change in logic state of numerous CMOS digital circuits during a memory write cycle. Write driver enable signals (ENT, ENC) and bitcell enable signals (WBC1-WBC24) are sequentially delayed in time during the write cycle through use of the propagation delay of inverters (INV1-INV24-7). The sequential time delay reduces the number of circuits that are simultaneously changing logic state at any given time during the write cycle. The power supply current transient is transformed from a single, large change in current to a series of smaller changes displaced in time from each other during the write cycle. The ground bounce of the power supply network attributed to the current transient is significantly reduced, such change in ground potential being directly related to the magnitude of the current transient and its rate of change with respect to time.
摘要翻译： 一种在存储器写入周期期间由许多CMOS数字电路的逻辑状态的同时改变引起的减少存储器阵列中的电源电流瞬变的方法。 通过使用逆变器（INV1-INV24-7）的传播延迟，写入周期期间写入驱动器使能信号（ENT，ENC）和位单元使能信号（WBC1-WBC24）在时间上顺序延迟。 顺序时间延迟减少了在写周期期间的任何给定时间同时改变逻辑状态的电路的数量。 在写周期期间，电源电流瞬变从单个大的电流变化转变为在时间上彼此偏移的一系列较小的变化。 归因于电流瞬变的电源网络的地面反弹明显减少，这种地电位的变化与当前瞬态的幅度及其相对于时间的变化率直接相关。
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公开(公告)号：US06799134B2
公开(公告)日：2004-09-28
申请号：US10216455
申请日：2002-08-09
IPC分类号： G06F1900
CPC分类号： G11C29/12015 , G01R31/3016 , G01R31/31725 , G01R31/318522 , G11C29/02 , G11C29/50012
摘要： A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit 2 in burst mode by detecting and measuring an output 15 of the self-timed sequential circuit 2.
摘要翻译： 一种用于通过检测和测量自定时序列电路2的输出15来验证突发模式中的自定时顺序电路2的突发模式操作和频率表征的方法和电路。
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公开(公告)号：US07210078B2
公开(公告)日：2007-04-24
申请号：US10230543
申请日：2002-08-29
CPC分类号： G11C29/003
摘要： A method for evaluating an output of a sequential circuit 2 by storing a series of output pulses from the sequential circuit 2 and determining whether the output pulses 4 toggled as desired. Also a circuit 1 for evaluating an output 4 of a sequential circuit 2 that determines if the output pulses 4 toggled as desired.
摘要翻译： 一种用于通过存储来自顺序电路2的一系列输出脉冲并确定输出脉冲4是否按需要切换来评估时序电路2的输出的方法。 还有一个用于评估顺序电路2的输出4的电路1，其确定输出脉冲4是否根据需要切换。
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公开(公告)号：US06414900B1
公开(公告)日：2002-07-02
申请号：US09998824
申请日：2001-12-03
IPC分类号： G11C800
摘要： A memory device (10) includes a memory array (12) having storage units (14) arranged in a plurality of rows (16). A row decoder (18) receives address information and determines which of the plurality of rows (16) to enable. According to the determined row (16), a row selector (20) drives the storage units (14) associated with the determined row (16) to provide their outputs onto respective bitlines (34) for identification by a bitline sensor (22). If the received address information indicates an out of range address that does not identify any of the plurality of rows (16) of the memory array (12), an out of range decoder (24) provides such determination to drive an out of range selector (26) to enable storage units (30) arranged in a single row (32) of a bitline driver (28). Outputs from the storage units (30) are applied to the respective bitlines (34) during an out of range address occurrence to prevent the bitlines (34) from being placed in an undesirable floating state.
摘要翻译： 存储器件（10）包括具有排列成多行（16）的存储单元（14）的存储器阵列（12）。 行解码器（18）接收地址信息并确定多个行（16）中的哪一行能够使能。 根据确定的行（16），行选择器（20）驱动与所确定的行（16）相关联的存储单元（14），以将它们的输出提供到相应的位线（34）上以供位线传感器（22）识别。 如果接收到的地址信息指示不识别存储器阵列（12）的多个行（16）中的任何一个的超出范围地址，则超出范围解码器（24）提供这样的确定以驱动超出范围选择器 （26），以使得能够布置在位线驱动器（28）的单行（32）中的存储单元（30）。 在超出范围地址发生期间，来自存储单元（30）的输出被施加到相应的位线（34），以防止位线（34）被置于不期望的浮动状态。
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