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    Partial CRC Insertion in Data Packets for Early Forwarding
    1.
    发明申请
    Partial CRC Insertion in Data Packets for Early Forwarding 有权
    数据包中的部分CRC插入用于提前转发

    公开(公告)号：US20080148135A1

    公开(公告)日：2008-06-19

    申请号：US11610219

    申请日：2006-12-13

    申请人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    发明人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    IPC分类号： G06F11/07

    CPC分类号： H04L1/0061 ,  H04L1/0079 ,  H04L1/1829 ,  H04L2001/0097

    摘要： In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.

    摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上发送的分组，所述分组包括命令和相关联的分组数据。 耦合到分组调度器并且被配置为在链路上传送分组，并且接口电路被配置为生成覆盖分组的错误检测数据。 接口电路被配置为在分组的末尾发送覆盖分组的错误检测数据，并且还被配置为在分组内插入至少一个部分错误检测数据。 部分错误检测数据覆盖部分错误检测数据之前的分组的一部分。 接收机被配置为接收数据并基于部分CRC校验转发数据。

    Command packet packing to mitigate CRC overhead
    2.
    发明授权
    Command packet packing to mitigate CRC overhead 有权
    命令包打包以减轻CRC开销

    公开(公告)号：US07881303B2

    公开(公告)日：2011-02-01

    申请号：US11610191

    申请日：2006-12-13

    申请人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    发明人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    IPC分类号： H04L12/56 ,  G06F11/00

    CPC分类号： H04L1/0011 ,  H04L1/0007 ,  H04L1/0061 ,  H04L1/18

    摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

    摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。

    Command Packet Packing to Mitigate CRC Overhead
    3.
    发明申请
    Command Packet Packing to Mitigate CRC Overhead 有权
    指令包打包以减轻CRC开销

    公开(公告)号：US20080148131A1

    公开(公告)日：2008-06-19

    申请号：US11610191

    申请日：2006-12-13

    申请人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    发明人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    IPC分类号： G06F11/07 ,  H03M13/00

    CPC分类号： H04L1/0011 ,  H04L1/0007 ,  H04L1/0061 ,  H04L1/18

    摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

    摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。

    Command packet packing to mitigate CRC overhead
    4.
    再颁专利
    Command packet packing to mitigate CRC overhead 有权
    命令包打包以减轻CRC开销

    公开(公告)号：USRE44487E1

    公开(公告)日：2013-09-10

    申请号：US13240272

    申请日：2011-09-22

    申请人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    发明人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    IPC分类号： H04L12/56 ,  G06F11/00 ,  H04B7/00

    CPC分类号： H04L1/0011 ,  H04L1/0007 ,  H04L1/0061 ,  H04L1/18

    摘要： In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

    摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上传送的分组以及耦合到分组调度器并被配置为在链路上传送分组的接口电路。 接口电路被配置为生成覆盖分组的错误检测数据，其中在链路上的分组之间传送错误检测数据。 接口电路被配置为通过一次错误检测数据的传输来覆盖多达N个分组，其中N是> = 2的整数。 由一个错误检测数据传输覆盖的分组的数量由接口电路确定，取决于要发送的分组的可用性。 在另一个实施例中，接口电路被配置为基于链路上消耗的带宽量来动态地改变链路上的错误检测数据的传输频率。

    Partial CRC insertion in data packets for early forwarding
    5.
    发明授权
    Partial CRC insertion in data packets for early forwarding 有权
    数据包中的部分CRC插入用于提前转发

    公开(公告)号：US07840873B2

    公开(公告)日：2010-11-23

    申请号：US11610219

    申请日：2006-12-13

    申请人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    发明人： William A. Hughes ,  Chen-Ping Yang ,  Greggory D. Donley ,  Michael K. Fertig

    IPC分类号： H03M13/00

    CPC分类号： H04L1/0061 ,  H04L1/0079 ,  H04L1/1829 ,  H04L2001/0097

    摘要： In an embodiment, a node comprises a packet scheduler configured to schedule a packet to be transmitted on the link, the packet comprising a command and associated packet data. Coupled to the packet scheduler and configured to transmit the packet on the link, and interface circuit is configured to generate error detection data covering the packet. The interface circuit is configured to transmit the error detection data covering the packet at an end of the packet, and is further configured to insert at least one partial error detection data within the packet. The partial error detection data covers a portion of the packet that precedes the partial error detection data. A receiver is configured to receive the data and forward the data based on partial CRC check.

    摘要翻译： 在一个实施例中，节点包括分组调度器，其被配置为调度要在链路上发送的分组，所述分组包括命令和相关联的分组数据。 耦合到分组调度器并且被配置为在链路上传送分组，并且接口电路被配置为生成覆盖分组的错误检测数据。 接口电路被配置为在分组的末尾发送覆盖分组的错误检测数据，并且还被配置为在分组内插入至少一个部分错误检测数据。 部分错误检测数据覆盖部分错误检测数据之前的分组的一部分。 接收机被配置为接收数据并基于部分CRC校验转发数据。

    Method and apparatus for selectively bypassing a cache for trace collection in a processor
    8.
    发明授权
    Method and apparatus for selectively bypassing a cache for trace collection in a processor 有权
    用于选择性地绕过高速缓存以用于处理器中的跟踪收集的方法和装置

    公开(公告)号：US08996816B2

    公开(公告)日：2015-03-31

    申请号：US12941576

    申请日：2010-11-08

    申请人： Greggory D. Donley ,  Benjamin Tsien ,  Vydhyanathan Kalyanasundharam ,  Patrick N. Conway ,  William A. Hughes

    发明人： Greggory D. Donley ,  Benjamin Tsien ,  Vydhyanathan Kalyanasundharam ,  Patrick N. Conway ,  William A. Hughes

    IPC分类号： G06F12/00 ,  G06F11/36 ,  G06F12/08

    CPC分类号： G06F11/3636 ,  G06F11/3648 ,  G06F12/0888

    摘要： A method and apparatus for selectively bypassing a cache in a processor of a computing device are disclosed. A mechanism to provide visibility to transactions on the core to a cache interface (e.g., an L3 cache interface) in a trace controller buffer (TCB) for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described. In an embodiment of the invention, there is provided a method for providing processing core request visibility comprising bypassing a higher level cache in response to a processing core request, capturing the processing core request in a TCB, providing a mask to filter the processing core request, and returning a transaction response to a requesting processing core.

    摘要翻译： 公开了一种用于选择性地绕过计算设备的处理器中的高速缓存的方法和装置。 通过引起缓存满足的选定事务，绕过控制器缓冲区（TCB）中的高速缓存接口（例如，L3缓存接口）来提供对核心上的事务的可见性的机制，以绕过 描述缓存并将其呈现给存储器系统，其中它们可以被登录在TCB中。 在本发明的实施例中，提供了一种用于提供处理核心请求可见性的方法，包括响应于处理核心请求绕过较高级别的高速缓存，在TCB中捕获处理核心请求，提供掩码以过滤处理核心请求 并将事务响应返回到请求处理核心。