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    Method and apparatus for selectively bypassing a cache for trace collection in a processor
    4.
    发明授权
    Method and apparatus for selectively bypassing a cache for trace collection in a processor 有权
    用于选择性地绕过高速缓存以用于处理器中的跟踪收集的方法和装置

    公开(公告)号：US08996816B2

    公开(公告)日：2015-03-31

    申请号：US12941576

    申请日：2010-11-08

    申请人： Greggory D. Donley ,  Benjamin Tsien ,  Vydhyanathan Kalyanasundharam ,  Patrick N. Conway ,  William A. Hughes

    发明人： Greggory D. Donley ,  Benjamin Tsien ,  Vydhyanathan Kalyanasundharam ,  Patrick N. Conway ,  William A. Hughes

    IPC分类号： G06F12/00 ,  G06F11/36 ,  G06F12/08

    CPC分类号： G06F11/3636 ,  G06F11/3648 ,  G06F12/0888

    摘要： A method and apparatus for selectively bypassing a cache in a processor of a computing device are disclosed. A mechanism to provide visibility to transactions on the core to a cache interface (e.g., an L3 cache interface) in a trace controller buffer (TCB) for debugging purposes, by causing selected transactions, which would otherwise be satisfied by the cache, to bypass the cache and be presented to the memory system where they may be logged in the TCB is described. In an embodiment of the invention, there is provided a method for providing processing core request visibility comprising bypassing a higher level cache in response to a processing core request, capturing the processing core request in a TCB, providing a mask to filter the processing core request, and returning a transaction response to a requesting processing core.

    摘要翻译： 公开了一种用于选择性地绕过计算设备的处理器中的高速缓存的方法和装置。 通过引起缓存满足的选定事务，绕过控制器缓冲区（TCB）中的高速缓存接口（例如，L3缓存接口）来提供对核心上的事务的可见性的机制，以绕过 描述缓存并将其呈现给存储器系统，其中它们可以被登录在TCB中。 在本发明的实施例中，提供了一种用于提供处理核心请求可见性的方法，包括响应于处理核心请求绕过较高级别的高速缓存，在TCB中捕获处理核心请求，提供掩码以过滤处理核心请求 并将事务响应返回到请求处理核心。

    Processor power management and method
    6.
    发明授权
    Processor power management and method 有权
    处理器电源管理和方法

    公开(公告)号：US08195887B2

    公开(公告)日：2012-06-05

    申请号：US12356624

    申请日：2009-01-21

    申请人： William A. Hughes ,  Kiran K. Bondalapati ,  Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Benjamin T. Sander

    发明人： William A. Hughes ,  Kiran K. Bondalapati ,  Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Benjamin T. Sander

    IPC分类号： G06F12/08 ,  G06F1/32

    CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F12/0808 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D50/20

    摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.

    摘要翻译： 公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。 当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。 如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。 在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。 因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。

    PROCESSOR POWER MANAGEMENT AND METHOD
    7.
    发明申请
    PROCESSOR POWER MANAGEMENT AND METHOD 有权
    处理器功率管理和方法

    公开(公告)号：US20100185820A1

    公开(公告)日：2010-07-22

    申请号：US12356624

    申请日：2009-01-21

    申请人： William A. Hughes ,  Kiran K. Bondalapati ,  Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Benjamin T. Sander

    发明人： William A. Hughes ,  Kiran K. Bondalapati ,  Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Benjamin T. Sander

    IPC分类号： G06F1/32 ,  G06F12/08

    CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F12/0808 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D50/20

    摘要： A data processing device is disclosed that includes multiple processing cores, where each core is associated with a corresponding cache. When a processing core is placed into a first sleep mode, the data processing device initiates a first phase. If any cache probes are received at the processing core during the first phase, the cache probes are serviced. At the end of the first phase, the cache corresponding to the processing core is flushed, and subsequent cache probes are not serviced at the cache. Because it does not service the subsequent cache probes, the processing core can therefore enter another sleep mode, allowing the data processing device to conserve additional power.

    摘要翻译： 公开了一种数据处理设备，其包括多个处理核心，其中每个核心与相应的高速缓存相关联。 当处理核心被置于第一睡眠模式时，数据处理设备启动第一阶段。 如果在第一阶段期间在处理核心处接收到任何高速缓存探测器，则对缓存探测器进行服务。 在第一阶段结束时，与处理核心相对应的高速缓冲存储器被刷新，并且后续高速缓存探测器不在缓存处被服务。 因为它不服务后续的缓存探测器，因此处理核心可以进入另一个睡眠模式，从而允许数据处理设备节省额外的功率。

    Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged
    9.
    发明授权
    Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged 有权
    处理节点包括多个处理器核和可配置成测试模式的互连，以使第一和第二事务源指示符互换

    公开(公告)号：US07165132B1

    公开(公告)日：2007-01-16

    申请号：US10956650

    申请日：2004-10-01

    申请人： Creigton S. Asato ,  Kevin J. McGrath ,  William A. Hughes ,  Vydhyanathan Kalyanasundharam

    发明人： Creigton S. Asato ,  Kevin J. McGrath ,  William A. Hughes ,  Vydhyanathan Kalyanasundharam

    IPC分类号： G06F13/00 ,  G06F9/46 ,  G06F19/00

    CPC分类号： G06F15/16

    摘要： In one embodiment, a processing node includes a plurality of processor cores and a reconfigurable interconnect. The processing node also includes a controller configured to schedule transactions received from each processor core. The interconnect may be coupled to convey between a first processor core and the controller, transactions that each include a first corresponding indicator that indicates the source of the transaction. The interconnect may also be coupled to convey transactions between a second processor core and the controller, transactions that each include a second corresponding indicator that indicates the source of the transaction. When operating in a first mode, the interconnect is configurable to cause the first indicator to indicate that the corresponding transactions were conveyed from the second processor core and to cause the second indicator to indicate that the corresponding transactions were conveyed from the first processor core.

    摘要翻译： 在一个实施例中，处理节点包括多个处理器核和可重配置互连。 处理节点还包括被配置为调度从每个处理器核心接收的事务的控制器。 互连可以被耦合以在第一处理器核心和控制器之间传送，每个事务包括指示事务源的第一对应指示符。 互连还可以被耦合以在第二处理器核心和控制器之间传送事务，每个事务包括指示事务源的第二对应指示符。 当以第一模式操作时，互连可配置为使得第一指示符指示相应的事务从第二处理器核心传送并使第二指示符指示对应的事务从第一处理器核心传送。

    Communicating between Partitions in a Statically Partitioned Multiprocessing System
    10.
    发明申请
    Communicating between Partitions in a Statically Partitioned Multiprocessing System 有权
    在静态分区多处理系统中分区间进行通信

    公开(公告)号：US20090037688A1

    公开(公告)日：2009-02-05

    申请号：US11831102

    申请日：2007-07-31

    申请人： Vydhyanathan Kalyanasundharam ,  William A. Hughes ,  Patrick Conway ,  Jeffrey Dwork

    发明人： Vydhyanathan Kalyanasundharam ,  William A. Hughes ,  Patrick Conway ,  Jeffrey Dwork

    IPC分类号： G06F12/06

    CPC分类号： G06F15/17

    摘要： In one embodiment, a method comprises assigning a unique node number to each of a first plurality of nodes in a first partition of a system and a second plurality of nodes in a second partition of the system. A first memory address space spans first memory included in the first partition and a second memory address space spans second memory included in the second partition. The first memory address space and the second memory address space are generally logically distinct. The method further comprises programming a first address map in the first partition to map the first memory address space to node numbers, wherein the programming comprises mapping a first memory address range within the first memory address space to a first node number assigned to a first node of the second plurality of nodes in the second partition, whereby the first memory address range is mapped to the second partition.

    摘要翻译： 在一个实施例中，一种方法包括向系统的第一分区中的第一多个节点和系统的第二分区中的第二多个节点中的每一个分配唯一的节点号。 第一存储器地址空间跨越包括在第一分区中的第一存储器，并且第二存储器地址空间跨越包括在第二分区中的第二存储器。 第一存储器地址空间和第二存储器地址空间通常在逻辑上是不同的。 该方法还包括编程第一分区中的第一地址映射以将第一存储器地址空间映射到节点号，其中编程包括将第一存储器地址空间内的第一存储器地址范围映射到分配给第一节点的第一节点号 的第二分区中的第二多个节点，由此第一存储器地址范围被映射到第二分区。