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    Chemical tobacco sucker control
    1.
    发明授权
    Chemical tobacco sucker control 失效
    化学烟草吸盘控制

    公开(公告)号：US4828601A

    公开(公告)日：1989-05-09

    申请号：US101324

    申请日：1987-09-25

    申请人： William Loh ,  Pawan K. Bassi

    发明人： William Loh ,  Pawan K. Bassi

    IPC分类号： A01N43/18 ,  C07D409/12

    CPC分类号： C07D409/12 ,  A01N43/18

    摘要： Methods and compositions for controlling tobacco suckers, which comprise administering an effective amount of certain 2-[1-[(5-chlorothien-2-yl)methoxyimino]ethyl]-3-hydroxy or alkanoyloxy-5-(tetrahydro-2H-thiopyran-3-yl)cyclohex-2-en-1-one derivatives to said tobacco plants or their growth medium.

    摘要翻译： 用于控制烟草吸盘的方法和组合物，其包括施用有效量的某些2- [1 - [（5-氯噻吩-2-基）甲氧基亚氨基]乙基] -3-羟基或烷酰氧基-5-（四氢-2H-噻喃） -3-基）环己-2-烯-1-酮衍生物加入到所述烟草植物或其生长培养基中。

    Row based analog standard cell layout design and methodology
    2.
    发明授权
    Row based analog standard cell layout design and methodology 有权
    基于行的模拟标准单元布局设计和方法

    公开(公告)号：US09292644B2

    公开(公告)日：2016-03-22

    申请号：US13572697

    申请日：2012-08-13

    申请人： William Loh ,  Erik Vaclav Chmelar

    发明人： William Loh ,  Erik Vaclav Chmelar

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G06F17/5063

    摘要： A system and method of designing the physical layout of an SoC incorporating row-based placement of analog standard cells whose heights are constrained to a predetermined row height or integer multiple thereof. A library of analog standard cells may be utilized by an ECAD tool to map, place, and route analog and mixed signal circuits in a manner similar to how such ECAD tool may utilize a library of digital standard cells to map, place, and route digital circuits. Mapping, placing, and routing of digital, analog, and mixed signal circuits may proceed within a unified ECAD SoC physical design flow. Finally, a general type analog standard cell is taught to further increase the speed and efficiency of analog and mixed-signal SoC layout.

    摘要翻译： 一种设计SoC的物理布局的系统和方法，该SoC包括将高度限制在其预定行高度或整数倍的模拟标准单元的基于行的放置。 模拟标准单元库可以被ECAD工具利用，以类似于这样的ECAD工具可以利用数字标准单元库来映射，放置和路由数字地图，放置和路由数字地图，放置和路由模拟和混合信号电路 电路。 数字，模拟和混合信号电路的映射，放置和布线可以在统一的ECAD SoC物理设计流程中进行。 最后，教授了通用型模拟标准单元，以进一步提高模拟和混合信号SoC布局的速度和效率。

    Systems and Methods for Synchronous, Retimed Analog to Digital Conversion
    3.
    发明申请
    Systems and Methods for Synchronous, Retimed Analog to Digital Conversion 有权
    用于同步，重定时模数转换的系统和方法

    公开(公告)号：US20100194616A1

    公开(公告)日：2010-08-05

    申请号：US12669481

    申请日：2008-06-06

    申请人： Erik Chmelar ,  Choshu Ito ,  William Loh

    发明人： Erik Chmelar ,  Choshu Ito ,  William Loh

    IPC分类号： H03M1/12

    CPC分类号： H03M1/1215 ,  H03M1/002 ,  H03M1/361

    摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.

    摘要翻译： 本发明的各种实施例提供了用于模数转换的系统和方法。 例如，公开了一种重新定时的模数转换器，其包括第一组子电平交织和第二组子电平交织。 第一组子电平交织包括与第一时钟相位同步的第一组比较器的第一子电平交织以及与第二时钟相位同步的第二组比较器的第二子电平交织。 第二组子电平交织包括与第三组比较器同步到第三时钟相位的第三子电平交织以及与第四时钟相位同步的第四组比较器的第四子电平交织。 至少部分地基于来自第二组子电平交织组的输出和第三组比较器中的一个，至少部分地基于第一组比较器的输出，选择第一组比较器中的一个， 子级交错。 在上述实施例的一些情况下，第一子电平交织的输出和第二子电平交织的输出被同步到第三时钟相位，并且第三子电平交织的输出和 第四子电平交错同步到第一时钟相位。

    Electrostatic Discharge Protection Circuit Employing a Micro Electro-Mechanical Systems (MEMS) Structure
    5.
    发明申请
    Electrostatic Discharge Protection Circuit Employing a Micro Electro-Mechanical Systems (MEMS) Structure 有权
    采用微机电系统（MEMS）结构的静电放电保护电路

    公开(公告)号：US20090296292A1

    公开(公告)日：2009-12-03

    申请号：US12128108

    申请日：2008-05-28

    申请人： Tze Wee Chen ,  William Loh ,  Choshu Ito

    发明人： Tze Wee Chen ,  William Loh ,  Choshu Ito

    IPC分类号： H02H9/00 ,  H01H59/00

    CPC分类号： H01H59/0009 ,  H02H9/046

    摘要： An ESD protection circuit for protecting a host circuit coupled to a signal pad from an ESD event occurring at the signal pad includes at least one MEMS switch which is electrically connected to the signal pad. The MEMS switch includes a first contact structure adapted for connection to the signal pad, and a second contact structure adapted for connection to a voltage supply source. The first and second contact structures are coupled together during the ESD event for shunting an ESD current from the signal pad to the voltage supply source. The first and second contact structures are electrically isolated from one another in the absence of the ESD event. At least one of the first and second contact structures includes a passivation layer for reducing contact adhesion between the first and second contact structures.

    摘要翻译： 用于保护耦合到信号垫的主机电路与在信号焊盘处发生的ESD事件的ESD保护电路包括至少一个电连接到信号焊盘的MEMS开关。 MEMS开关包括适于连接到信号焊盘的第一接触结构和适于连接到电压源的第二接触结构。 在ESD事件期间，第一和第二接触结构耦合在一起，用于将ESD电流从信号焊盘分流到电压源。 在没有ESD事件的情况下，第一和第二接触结构彼此电隔离。 第一和第二接触结构中的至少一个包括用于减小第一和第二接触结构之间的接触粘附的钝化层。