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    HIGH-SPEED DEBUG PORT TRACE CIRCUIT
    1.
    发明公开
    HIGH-SPEED DEBUG PORT TRACE CIRCUIT 审中-公开

    公开(公告)号：US20240330145A1

    公开(公告)日：2024-10-03

    申请号：US18193488

    申请日：2023-03-30

    Applicant: Xilinx, Inc.

    Inventor： Elessar Taggart ,  Ishita Ghosh ,  Rishi Bharadwaj Subramanian

    IPC: G06F11/34

    CPC classification number: G06F11/348 ,  G06F11/3476

    Abstract: An integrated circuit includes a high-speed debug port trace circuit. The high-speed debug trace circuit includes a plurality of input receiver circuits each configured to receive a stream of trace data. The plurality of input receiver circuits receive streams of trace data from a plurality of compute circuits of different compute circuit types. The plurality of compute circuits are within the integrated circuit. The high-speed debug trace circuit includes a stream selector circuit configured to perform multiple stages of arbitration among the plurality of streams of trace data to generate output trace data. The stream selector circuit inserts compute circuit type identifiers within the output trace data. Each compute circuit type identifier specifies a compute circuit type that originated each portion of trace data of the output trace data. The high-speed debug trace circuit includes an output transmitter circuit configured to output the output trace data.

    HIGH-SPEED OFFLOADING OF TRACE DATA FROM AN INTEGRATED CIRCUIT
    3.
    发明公开
    HIGH-SPEED OFFLOADING OF TRACE DATA FROM AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20240330144A1

    公开(公告)日：2024-10-03

    申请号：US18193444

    申请日：2023-03-30

    Applicant: Xilinx, Inc.

    Inventor： Ishita Ghosh ,  Elessar Taggart ,  Rishi Bharadwaj Subramanian ,  Jason Richard Villarreal

    IPC: G06F11/34

    CPC classification number: G06F11/348 ,  G06F11/3476

    Abstract: Offloading trace data from an integrated circuit (IC) can include receiving, by a high-speed debug port (HSDP) trace circuit, streams of trace data from a plurality of compute circuits of different compute circuit types. The compute circuits and the HSDP trace circuit are disposed in a same IC. Compute circuit type identifiers are included within the trace data. The compute circuit type identifiers specify the compute circuit type from which respective ones of the streams of the trace data originate. Debug trace packets (DTPs) are generated from the trace data and transmitted over a high-speed communication link to a trace data storage device (TDSD) external to the IC. Within the TDSD, trace data from the DTPs are stored in a memory of the TDSD.

    Mixed-language simulation
    5.
    发明授权
    Mixed-language simulation 有权

    公开(公告)号：US10296673B1

    公开(公告)日：2019-05-21

    申请号：US14723188

    申请日：2015-05-27

    Applicant: Xilinx, Inc.

    Inventor： Ishita Ghosh ,  Hem C. Neema ,  Jason Villarreal ,  Saikat Bandyopadhyay ,  Kumar Deepak

    IPC: G06F17/50

    Abstract: For generating code for simulation of a circuit design, a hardware description language (HDL) description and a high-level language (HLL) description of portions of the circuit design are input. The HLL description specifies a first function and the HDL description includes a call to the first function. A wrapper is generated for the first function. The wrapper has an associated stack frame and includes code that stores in the stack frame values of arguments specified by the call to the first function and code that calls the first function. An HLL simulation specification is generated from the HDL description. The HLL simulation specification includes a call to the first HLL wrapper in place of the call to the first function. The HLL simulation specification, the first HLL wrapper, and the HLL description are compiled into executable program code.

    Performance and memory efficient modeling of HDL ports for simulation
    6.
    发明授权
    Performance and memory efficient modeling of HDL ports for simulation 有权
    HDL端口的性能和内存高效建模用于仿真

    公开(公告)号：US09223910B1

    公开(公告)日：2015-12-29

    申请号：US14159855

    申请日：2014-01-21

    Applicant: Xilinx, Inc.

    Inventor： Ishita Ghosh ,  Saikat Bandyopadhyay ,  Kumar Deepak ,  Hem C. Neema ,  David K. Liddell

    IPC: G06F17/50

    CPC classification number: G06F17/5022

    Abstract: A method for compiling an HDL specification for simulation of a circuit design is disclosed. The circuit design is elaborated from the HDL specification and memory locations are allocated for formals and actuals of the elaborated circuit design. For each port having a formal and an actual that are compatible, the allocating of memory locations sets a reference pointer for the formal and a reference pointer for the actual to reference a same one of the memory locations. For each port having a formal and an actual that are incompatible, the allocating of memory locations sets the reference pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations. Simulation code modeling the elaborated circuit design is generated that updates a formal and actual of a port that are compatible using a single write operation to the referenced memory location.

    Abstract translation: 公开了一种用于编译用于模拟电路设计的HDL规范的方法。 电路设计由HDL规范进行阐述，内存位置分配给精密电路设计的正式和实际。 对于具有兼容的形式和实际的每个端口，存储器位置的分配设置用于形式的参考指针和用于实际引用相同存储器位置的引用指针。 对于具有不兼容的形式和实际的每个端口，存储器位置的分配设置形式的参考指针和用于实际引用的参考指针以引用不同的相应存储器位置。 生成针对详细电路设计的仿真代码建模，其将使用单个写入操作兼容的端口的正式和实际更新到引用的存储器位置。

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