公开(公告)号：US10482054B1

公开(公告)日：2019-11-19

申请号：US15261626

申请日：2016-09-09

Applicant: Xilinx, Inc.

Inventor： Ling Liu ,  Michaela Blott ,  Kimon Karras ,  Thomas Janson ,  Kornelis A. Vissers

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38 ,  H04L12/861

Abstract: The coherent accelerator processor interface (CAPI) provides a high-performance when using heterogeneous compute architectures, but CAPI is not compatible with the advanced extensible interface (AXI) which is used by many accelerators. The examples herein describe an AXI-CAPI adapter (e.g., a hardware architecture) that converts AXI signals to CAPI signals and vice versus. In one example, the AXI-CAPI adapter includes four modules: a low-level shim, a high-level shim, an AXI full module, and an AXI Lite module which are organized in a hierarchy of hardware elements. Each of the modules outputs can output a different version of the AXI signals using the hierarchical structure.

公开(公告)号：US10320918B1

公开(公告)日：2019-06-11

申请号：US14574283

申请日：2014-12-17

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  David A. Sidler ,  Kimon Karras ,  Raymond Carley ,  Kornelis A. Vissers

IPC: G06F15/16 ,  H04L29/08 ,  H04L12/741

Abstract: In an example, an integrated circuit (IC) includes a receive circuit, a transmit circuit, and a control circuit. The receive circuit includes a receive data path and a receive control interface, the receive data path coupled to store received transmission control protocol (TCP) data for a plurality of TCP sessions in a respective plurality of receive buffers in an external memory circuit external to the IC. The transmit circuit includes a transmit data path and a transmit control interface, the transmit data path coupled to read TCP data to be transmitted for the plurality of TCP sessions from a respective plurality of transmit buffers in the external memory circuit. The control circuit is coupled to the receive control interface and the transmit control interface, the control circuit configured to maintain data structures to maintain TCP state information for the plurality of TCP sessions.

公开(公告)号：US20150311899A1

公开(公告)日：2015-10-29

申请号：US14260580

申请日：2014-04-24

Applicant: Xilinx, Inc.

Inventor： Kimon Karras ,  Michaela Blott ,  Kornelis A. Vissers

IPC: H03K19/177 ,  G06F17/50

CPC classification number: H03K19/17748 ,  G06F17/5054 ,  G06F17/5068 ,  H03K19/17724

Abstract: A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.

Abstract translation: 可编程IC包括多个可编程资源，耦合到多个可编程资源的多个可共享逻辑电路和虚拟化电路。 多个可编程资源包括可编程逻辑电路和可编程路由资源。 虚拟化电路被配置为管理在多个可编程资源中实现的多个用户设计之间的多个可共享逻辑电路的共享。 用户设计在可编程IC上彼此通信隔离。

公开(公告)号：US20250147799A1

公开(公告)日：2025-05-08

申请号：US18501868

申请日：2023-11-03

Applicant: Xilinx, Inc.

Inventor： Thomas Calvert ,  Ripduman Sohan ,  Dmitri Kitariev ,  Kimon Karras ,  Stephan Diestelhorst ,  Neil Turton ,  David Riddoch ,  Derek Roberts ,  Kieran Mansley ,  Steven Pope

IPC: G06F9/48

Abstract: A computer-implemented method for task management can include managing performance of a task on a message by a plurality of circuits. In some aspects, the task can comprise a sequence of processings to be performed on the message and each circuit of the plurality of circuits performing a processing of the sequence of processings. In some aspects, the method can include routing, based on the sequence, a first information regarding the task to a first circuit of the plurality of circuits to perform a first processing of the sequence of processings on the message; receiving, from the first circuit, an output of the first processing; and routing, based on the sequence of processings identified for the task, a second information regarding the task to a second circuit of the plurality of circuits to perform a second processing that follows the first processing in the sequence of processings.

公开(公告)号：US10482129B1

公开(公告)日：2019-11-19

申请号：US15484455

申请日：2017-04-11

Applicant: Xilinx, Inc.

Inventor： Michaela Blott ,  Ling Liu ,  Daniel Ziener ,  Kimon Karras

IPC: G06F7/02 ,  G06F16/00 ,  G06F16/9038 ,  G06F3/06 ,  G06F16/93 ,  G06F16/901 ,  G06F16/903

Abstract: Disclosed approaches for accessing data involve determining in a first stage of a pipelined processing circuit, hash values from keys in a data access request and determining in a second stage of the pipelined processing circuit and from a hash table, addresses associated with the hash values. In a third stage of the pipelined processing circuit, data are read at the addresses in a memory arrangement, and in a fourth stage of the pipelined processing circuit a subset of the data read from the memory arrangement is selected according to a query in the data access request. In a fifth stage of the pipelined processing circuit, the subset of the data read from the memory arrangement is merged into response data.

公开(公告)号：US09503093B2

公开(公告)日：2016-11-22

申请号：US14260580

申请日：2014-04-24

Applicant: Xilinx, Inc.

Inventor： Kimon Karras ,  Michaela Blott ,  Kornelis A. Vissers

IPC: G06F17/50 ,  H03K19/177

CPC classification number: H03K19/17748 ,  G06F17/5054 ,  G06F17/5068 ,  H03K19/17724

Abstract: A programmable IC includes a plurality of programmable resources, a plurality of shareable logic circuits coupled to the plurality of programmable resources, and a virtualization circuit. The plurality of programmable resources includes programmable logic circuits and programmable routing resources. The virtualization circuit is configured to manage sharing of the plurality of shareable logic circuits between a plurality of user designs implemented in the plurality of programmable resources. The user designs are communicatively isolated from one another on the programmable IC.

Abstract translation: 可编程IC包括多个可编程资源，耦合到多个可编程资源的多个可共享逻辑电路和虚拟化电路。 多个可编程资源包括可编程逻辑电路和可编程路由资源。 虚拟化电路被配置为管理在多个可编程资源中实现的多个用户设计之间的多个可共享逻辑电路的共享。 用户设计在可编程IC上彼此通信隔离。