公开(公告)号：US09009577B1

公开(公告)日：2015-04-14

申请号：US13676043

申请日：2012-11-13

Applicant: Xilinx, Inc.

Inventor： Hai-Jo Tarn ,  Krishna R. Narayanan ,  Raghavendar M. Rao ,  Raied N. Mazahreh

IPC: H03M13/15

CPC classification number: H03M13/1555 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/1575 ,  H03M13/2909 ,  H03M13/2921 ,  H03M13/293 ,  H03M13/2948 ,  H03M13/616

Abstract: A decoding circuit is disclosed that includes a decoding pipeline configured to receive a data block that includes a plurality of data symbols, encoded with a Reed-Solomon (RS) FEC coding thereafter further encoded by a second FEC coding. The data block also includes a first and second sets of FEC datagrams for correcting received words of the plurality of data symbols encoded with the RS FEC coding and second FEC coding, respectively. Each decoding stage of the pipeline is configured to decode the plurality of data symbols using the first and second sets of FEC datagrams. A post-processing circuit connected to an output of the pipelines is configured to perform bitwise RS decoding of ones of the plurality of data symbols in error.

Abstract translation: 公开了一种解码电路，其包括解码流水线，该解码流水线被配置为接收包含多个数据符号的数据块，所述多个数据符号被随后由第二FEC编码编码的里德 - 所罗门（RS）FEC编码进行编码。 数据块还包括第一和第二组FEC数据报，用于分别用于校正用RS FEC编码和第二FEC编码编码的多个数据符号的接收字。 流水线的每个解码级被配置为使用第一和第二组FEC数据报对多个数据符号进行解码。 连接到管线输出端的后处理电路被配置为对多个数据符号中的一个进行按位RS解码错误。

公开(公告)号：US09287899B1

公开(公告)日：2016-03-15

申请号：US14137812

申请日：2013-12-20

Applicant: Xilinx, Inc.

Inventor： Raied N. Mazahreh ,  Raghavendar M. Rao ,  Krishna R. Narayanan ,  Henry D. Pfister

IPC: H03M13/27

CPC classification number: H03M13/2927 ,  H03M13/152 ,  H03M13/2921

Abstract: Methods and circuits are disclosed for forward-error-correction (FEC) decoding. A plurality of symbols are received in an interleaved format of rows and columns of the symbols. A plurality of FEC decoding iterations are performed on the plurality of symbols. Each decoding iteration performs FEC decoding of the rows of the plurality of symbols and performs FEC decoding of the columns of the plurality of symbols. After performing the decoding iterations, rows in error and columns in error of the plurality of symbols are determined. In response to the determined rows in error and the determined columns in error matching a deadlock pattern, symbols at intersections of the determined rows and columns in error are determined. Bits of one or more symbols of the determined symbols are inverted. After the inverting of the bits, one or more of the FEC decoding iterations are performed.

Abstract translation: 公开了用于前向纠错（FEC）解码的方法和电路。 以符号的行和列的交错格式接收多个符号。 对多个符号执行多个FEC解码迭代。 每个解码迭代执行多个符号的行的FEC解码，并对多个符号的列执行FEC解码。 在执行解码迭代之后，确定错误的行和多个符号的错误列。 响应于确定的错误行和确定的错误匹配死锁模式的列，确定所确定的行和错误列的交点处的符号。 所确定的符号的一个或多个符号的位被反转。 在比特反转之后，执行一个或多个FEC解码迭代。

公开(公告)号：US09083383B1

公开(公告)日：2015-07-14

申请号：US13752689

申请日：2013-01-29

Applicant: Xilinx, Inc.

Inventor： Nihat E. Tunali ,  Raghavendar M. Rao ,  Raied N. Mazahreh ,  Krishna R. Narayanan

IPC: H03M13/00 ,  H03M13/13

CPC classification number: H03M13/13 ,  H03M13/036 ,  H03M13/112 ,  H03M13/1197 ,  H03M13/6502

Abstract: An apparatus is disclosed. In this apparatus, at least one coder block has a parity check matrix. The parity check matrix comprises each element of an H matrix expanded by a Progressive Edge Growth (“PEG”) expansion factor and an Approximate Cycle Extrinsic Message Degree (“ACE”) expansion factor.

Abstract translation: 公开了一种装置。 在该装置中，至少一个编码器块具有奇偶校验矩阵。 奇偶校验矩阵包括通过渐进边缘增长（“PEG”）扩展因子和近似周期外在消息度（“ACE”）扩展因子扩展的H矩阵的每个元素。

公开(公告)号：US09203440B1

公开(公告)日：2015-12-01

申请号：US13752718

申请日：2013-01-29

Applicant: Xilinx, Inc.

Inventor： Nihat E. Tunali ,  Raghavendar M. Rao ,  Raied N. Mazahreh ,  Krishna R. Narayanan

IPC: H03M13/11 ,  H03M13/29 ,  H03M13/53 ,  H03M13/03

CPC classification number: H03M13/2906 ,  H03M13/033 ,  H03M13/116 ,  H03M13/1188 ,  H03M13/1197 ,  H03M13/6325 ,  H03M13/6362

Abstract: A method for matrix expansion is disclosed. In this method, a Progressive Edge Growth (“PEG”) expanding of an H matrix by a coder is used to provide an expanded H matrix. An Approximate Cycle Extrinsic Message Degree (“ACE”) expanding of the expanded H matrix by the coder is used to provide a parity check matrix for a code. The ACE expanding includes initializing a first index to increment in a first range associated with a PEG expansion factor, expanding each non-zero element in the expanded H matrix with a random shifted identity matrix for the first range, initializing a second index to increment in a second range associated with the first index and an ACE expansion factor, and performing an ACE detection for each variable node in the second range for the variable nodes of the parity check matrix. The coder outputs information using the parity check matrix.

Abstract translation: 公开了一种用于矩阵扩展的方法。 在该方法中，使用编码器对H矩阵的渐进边缘增长（“PEG”）进行扩展以提供扩展的H矩阵。 使用由编码器扩展的H矩阵的近似周期外部消息度（“ACE”）来提供用于代码的奇偶校验矩阵。 ACE扩展包括初始化第一索引以在与PEG扩展因子相关联的第一范围内增加，以扩展的H矩阵中的每个非零元素以第一范围的随机移位单位矩阵进行扩展，初始化第二索引以递增 与第一索引和ACE扩展因子相关联的第二范围，以及针对奇偶校验矩阵的可变节点的第二范围中的每个变量节点执行ACE检测。 编码器使用奇偶校验矩阵输出信息。

公开(公告)号：US08959418B1

公开(公告)日：2015-02-17

申请号：US13691501

申请日：2012-11-30

Applicant: Xilinx, Inc.

Inventor： Henry D. Pfister ,  Krishna R. Narayanan ,  Raied N. Mazahreh ,  Raghavendar M. Rao

IPC: H03M13/00 ,  H03M13/05

CPC classification number: H03M13/2906 ,  H03M13/152 ,  H03M13/2921 ,  H03M13/2948

Abstract: In one embodiment, a circuit for FEC decoding includes first and second syndrome calculation circuits, configured to calculate FEC syndromes for rows and columns of symbols in a de-interleaved format, respectively. A decoding circuit is configured to arrange the symbols into windows. Each window includes a plurality of sequential rows and sequential columns of the symbols in the de-interleaved format. The decoding circuit is configured to place N of the windows in a group and perform M decoding iterations of the windows in the group. In each decoding iteration, the decoding circuit performs FEC decoding of rows of each of the windows in the group followed by FEC decoding of columns of each of the windows in the group.

Abstract translation: 在一个实施例中，用于FEC解码的电路包括第一和第二校正子计算电路，被配置为分别以解交错格式计算行和列符号的FEC校验子。 解码电路被配置为将符号布置成窗口。 每个窗口包括解交织格式的多个顺序行和符号的顺序列。 解码电路被配置为将N个窗口放置在组中，并对该组中的窗口执行M个解码迭代。 在每个解码迭代中，解码电路对组中的每个窗口的行进行FEC解码，接着对组中的每个窗口的列进行FEC解码。