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公开(公告)号：US09967057B1
公开(公告)日：2018-05-08
申请号：US15345353
申请日：2016-11-07
Applicant: Xilinx, Inc.
Inventor： Nihat E. Tunali , Michael Wu , Hai-Jo Tarn , Christopher H. Dick
CPC classification number: H04L1/0045 , G06F17/10 , H04L25/067
Abstract: A method includes communicating data in a channel. Received symbols for the data correspond to points of a received symbol space respectively. First and second dimensions of the received symbol space correspond to a real part and an imaginary part of the received symbols respectively. A first received symbol for the data is obtained. A first region of the received symbol space for the first received symbol is determined. A first regression model associated with the first region and a first bit of the first received symbol is retrieved from a storage. The first regression model includes a plurality of regressors. A first log-likelihood ratio (LLR) for the first bit of the first received symbol is estimated using the first regression model.
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公开(公告)号：US09009577B1
公开(公告)日：2015-04-14
申请号：US13676043
申请日：2012-11-13
Applicant: Xilinx, Inc.
Inventor： Hai-Jo Tarn , Krishna R. Narayanan , Raghavendar M. Rao , Raied N. Mazahreh
IPC: H03M13/15
CPC classification number: H03M13/1555 , H03M13/1515 , H03M13/152 , H03M13/1575 , H03M13/2909 , H03M13/2921 , H03M13/293 , H03M13/2948 , H03M13/616
Abstract: A decoding circuit is disclosed that includes a decoding pipeline configured to receive a data block that includes a plurality of data symbols, encoded with a Reed-Solomon (RS) FEC coding thereafter further encoded by a second FEC coding. The data block also includes a first and second sets of FEC datagrams for correcting received words of the plurality of data symbols encoded with the RS FEC coding and second FEC coding, respectively. Each decoding stage of the pipeline is configured to decode the plurality of data symbols using the first and second sets of FEC datagrams. A post-processing circuit connected to an output of the pipelines is configured to perform bitwise RS decoding of ones of the plurality of data symbols in error.
Abstract translation: 公开了一种解码电路，其包括解码流水线，该解码流水线被配置为接收包含多个数据符号的数据块，所述多个数据符号被随后由第二FEC编码编码的里德 - 所罗门（RS）FEC编码进行编码。 数据块还包括第一和第二组FEC数据报，用于分别用于校正用RS FEC编码和第二FEC编码编码的多个数据符号的接收字。 流水线的每个解码级被配置为使用第一和第二组FEC数据报对多个数据符号进行解码。 连接到管线输出端的后处理电路被配置为对多个数据符号中的一个进行按位RS解码错误。
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公开(公告)号：US10263644B1
公开(公告)日：2019-04-16
申请号：US14925825
申请日：2015-10-28
Applicant: Xilinx, Inc.
Inventor： Raied N. Mazahreh , Hai-Jo Tarn , Nihat E. Tunali , Christopher H. Dick
Abstract: Methods and systems are presented in this disclosure for implementing forward error correction in cloud and data center storage devices based on low-density parity-check (LDPC) channel coding. A forward error correction circuit presented herein includes a first LDPC decoder configured to perform hard-decision LDPC decoding of data read from a storage medium through a first read channel. The forward error correction circuit further includes a hybrid LDPC decoder selectively configurable to perform a selected one of hard-decision LDPC decoding and soft-decision LDPC decoding of data read from the storage medium through a second read channel, wherein, responsive to a control signal generated based, at least in part, on one or more parameters indicative of condition of the storage medium, the hybrid LDPC decoder is switchable between hard-decision LDPC decoding and soft-decision LDPC decoding.
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Patent Agency Ranking
公开(公告)号：US09667276B1
公开(公告)日：2017-05-30
申请号：US14820430
申请日：2015-08-06
Applicant: Xilinx, Inc.
Inventor： Nihat E. Tunali , Raied N. Mazahreh , Hai-Jo Tarn
CPC classification number: H03M13/616 , H03M13/1102 , H03M13/116 , H03M13/118
Abstract: A system for providing data encoding includes: an encoder configured to encode message data with an encoding parity-check matrix having a parity part that is in lower-triangular form to generate an encoded message data, the encoded message data being for decoded by a decoder; wherein the encoding parity-check matrix is based on a decoding parity-check matrix that does not comprise any degree-1 node in a parity part of the decoding parity-check matrix; and wherein the system further comprises a non-transitory medium for storing the encoding parity-check matrix, wherein the non-transitory medium is a part of the encoder or is communicatively coupled to the encoder.
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公开(公告)号：US09047241B2
公开(公告)日：2015-06-02
申请号：US13751929
申请日：2013-01-28
Applicant: Xilinx, Inc.
Inventor： Raied N. Mazahreh , Hai-Jo Tarn , Raghavendar M. Rao
CPC classification number: G06F17/16 , G06F7/78 , G06F15/8046 , H04B7/0413 , H04B7/0854 , H04L25/0244
Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.
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公开(公告)号：US09047240B2
公开(公告)日：2015-06-02
申请号：US13751881
申请日：2013-01-28
Applicant: Xilinx, Inc.
Inventor： Raied N. Mazahreh , Hai-Jo Tarn , Raghavendar M. Rao
CPC classification number: G06F17/16 , G06F7/78 , G06F15/8046 , H04B7/0413 , H04B7/0854 , H04L25/0244
Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.
Abstract translation: 第一收缩阵列从多个信道矩阵接收时分多路复用矩阵的输入集合。 在第一模式中，第一收缩阵列在输入矩阵上执行三角化，产生第一组矩阵，并且在第二模式中对第一集合执行反替代，产生第二组矩阵。 在第一模式中，第二收缩阵列利用输入的矩阵集在第二组矩阵上执行左乘法，产生第三组矩阵。 在第二模式中，第二收缩阵列在第三组矩阵上执行交叉对角线转置，产生第四组矩阵，并且在具有第四组矩阵的第二组矩阵上执行右乘法。 第一收缩阵列在三角化后从第一模式切换到第二模式，并且第二收缩阵列在左乘法之后从第一模式切换到第二模式。
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公开(公告)号：US20130144926A1
公开(公告)日：2013-06-06
申请号：US13751929
申请日：2013-01-28
Applicant: XILINX, INC.
Inventor： Raied N. Mazahreh , Hai-Jo Tarn , Raghavendar M. Rao
IPC: G06F17/16
CPC classification number: G06F17/16 , G06F7/78 , G06F15/8046 , H04B7/0413 , H04B7/0854 , H04L25/0244
Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.
Abstract translation: 第一收缩阵列从多个信道矩阵接收时分多路复用矩阵的输入集合。 在第一模式中，第一收缩阵列在输入矩阵上执行三角化，产生第一组矩阵，并且在第二模式中对第一集合执行反替代，产生第二组矩阵。 在第一模式中，第二收缩阵列利用输入的矩阵集在第二组矩阵上执行左乘法，产生第三组矩阵。 在第二模式中，第二收缩阵列在第三组矩阵上执行交叉对角线转置，产生第四组矩阵，并且在具有第四组矩阵的第二组矩阵上执行右乘法。 第一收缩阵列在三角化后从第一模式切换到第二模式，并且第二收缩阵列在左乘法之后从第一模式切换到第二模式。
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公开(公告)号：US20130138712A1
公开(公告)日：2013-05-30
申请号：US13751881
申请日：2013-01-28
Applicant: XILINX, INC.
Inventor： Raied N. Mazahreh , Hai-Jo Tarn , Raghavendar M. Rao
IPC: G06F17/16
CPC classification number: G06F17/16 , G06F7/78 , G06F15/8046 , H04B7/0413 , H04B7/0854 , H04L25/0244
Abstract: A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode performs back-substitution on the first set, producing a second set of matrices. In a first mode, a second systolic array performs left multiplication on the second set of matrices with the input set of matrices, producing a third set of matrices. In a second mode, the second systolic array performs cross diagonal transposition on the third set of matrices, producing a fourth set of matrices, and performs right multiplication on the second set of matrices with the fourth set of matrices. The first systolic array switches from the first mode to the second mode after the triangularization, and the second systolic array switches from the first mode to the second mode after the left multiplication.
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