公开(公告)号：US10664561B1

公开(公告)日：2020-05-26

申请号：US15729483

申请日：2017-10-10

Applicant: Xilinx, Inc.

Inventor： Pradip K. Kar ,  Satyaprakash Pareek ,  Shangzhi Sun ,  Bing Tian

IPC: G06F17/50

Abstract: Disclosed approaches of pipelining cascaded memory blocks include determining memory blocks combined to implement a memory in a netlist of a circuit design. A model of the memory blocks arranged in a matrix is generated and a total number of delay registers that can be inserted between an input and an output of the memory is determined based on an input latency constraint. For each column, positions of delay registers are determined between an input of the column and the output of the memory. The circuit design is modified to include the delay registers at the determined positions.

公开(公告)号：US10606979B1

公开(公告)日：2020-03-31

申请号：US16001206

申请日：2018-06-06

Applicant: Xilinx, Inc.

Inventor： Shangzhi Sun ,  Bing Tian ,  Chaithanya Dudha

IPC: G06F17/50

Abstract: Verifying a circuit design may include, in response to modification of the circuit design involving at least one of inserting or removing a flip-flop, determining, using computer hardware, latency change values for pins of components of the circuit design, determining, using the computer hardware, total latency for the pins of the components of the circuit design based, at least in part, upon the latency change values, and comparing, using the computer hardware, total latency of the pins of the components of the circuit design. Verifying the circuit design may also include detecting, using the computer hardware, a latency error within the circuit design based upon the comparing and generating, using the computer hardware, a notification of the latency error in the circuit design, wherein the notification specifies a type of the latency error detected.

公开(公告)号：US10678983B1

公开(公告)日：2020-06-09

申请号：US15987372

申请日：2018-05-23

Applicant: Xilinx, Inc.

Inventor： Shangzhi Sun ,  Chaithanya Dudha ,  Bing Tian ,  Ashish Sirasao

IPC: G06F30/3312 ,  G06F30/30 ,  G06F111/20 ,  G06F119/12

Abstract: Local retiming for a circuit design includes determining, using computer hardware, a load of a synchronous circuit element within the circuit design tagged for forward retiming, traversing, using the computer hardware, each input of the load backward through the circuit design until a sequential circuit element or a primary input is reached, and adding, using the computer hardware, each synchronous circuit element encountered in the traversing to a forward retiming list. In response to determining that forward retiming criteria is met for the forward retiming list, the computer hardware modifies the circuit design by creating a new synchronous circuit element at an output of the load.

公开(公告)号：US10303833B1

公开(公告)日：2019-05-28

申请号：US15429014

申请日：2017-02-09

Applicant: Xilinx, Inc.

Inventor： Aman Gayasen ,  Surya Pratik Saha ,  Elliott Delaye ,  Shangzhi Sun ,  Ashish Sirasao

IPC: G06F17/50

Abstract: Parallelizing operations for implementing a circuit design can include dividing, using a processor, the circuit design into a plurality of partitions, wherein each partition is stored as a separate file, for each partition, generating, using the processor, a timing arc file specifying boundary delays for the partition, and generating, using the processor, a partition design file specifying interfaces of the partitions. Using the processor, a plurality of processes executing in parallel can be initiated. Each process is adapted to operate on a selected partition using the partition design file and the timing arc files for the other partitions to generate an updated file for the selected partition.

公开(公告)号：US10289786B1

公开(公告)日：2019-05-14

申请号：US15634016

申请日：2017-06-27

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Shangzhi Sun ,  Ashish Sirasao ,  Nithin Kumar Guggilla

IPC: G06F17/50

Abstract: Reducing latency of a circuit design can include determining, using a processor, a set of sequential circuit elements of a circuit design that meets a condition for removal from the circuit design, wherein the condition is dependent upon a target technology process and a target operating frequency. Using the processor, a feasible cut for a selected sequential circuit element of the set is determined. The selected sequential circuit element and each other sequential circuit element of the set that is part of the cut is removed from the circuit design using the processor.

公开(公告)号：US20240256749A1

公开(公告)日：2024-08-01

申请号：US18102490

申请日：2023-01-27

Applicant: Xilinx, Inc.

Inventor： Chaithanya Dudha ,  Ruibing Lu ,  Shangzhi Sun ,  Nithin Kumar Guggilla

IPC: G06F30/3312 ,  G06F30/392 ,  G06F30/394

CPC classification number: G06F30/3312 ,  G06F30/392 ,  G06F30/394 ,  G06F2119/12

Abstract: Retiming a circuit design can include determining whether or not an initial value specified for a candidate register can be removed based on an input logic cone to the candidate register and an output logic cone from the candidate register. The candidate register is a register in a critical path in the circuit design. The candidate register can be retimed into a retimed register in response to determining that the initial value specified for the candidate register can be removed. A new initial value for the retimed register can be derived based on initial values of registers in a logic cone of the retimed register, and the new initial value can be assigned to the retimed register.