公开(公告)号：US11652481B2

公开(公告)日：2023-05-16

申请号：US17405073

申请日：2021-08-18

Applicant: XILINX, INC.

Inventor： Pierre Maillard ,  Betty Lau ,  Yanran Chen ,  Jun Liu ,  Martin L. Voogel

IPC: H03K19/003 ,  G06F30/392 ,  H03K19/20 ,  H03K3/0233 ,  G06F30/30

CPC classification number: H03K19/003 ,  G06F30/30 ,  G06F30/392 ,  H03K3/0233 ,  H03K19/20

Abstract: One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

公开(公告)号：US10574214B1

公开(公告)日：2020-02-25

申请号：US16137405

申请日：2018-09-20

Applicant: Xilinx, Inc.

Inventor： Pierre Maillard ,  Yanran Chen ,  Michael J. Hart

IPC: H03K3/037 ,  H03K19/17764 ,  H03K19/1776 ,  H03K19/177 ,  H03K3/3562

Abstract: A circuit for storing data in an integrated circuit is described. The circuit comprises an input adapted to receive the data; a memory element coupled to the input, the memory element comprising a storage node for storing the data; at least one node that is separate from the storage node for storing the data; and at least a portion of a dummy transistor coupled to the at least one node that is separate from the storage node for storing the data. A method of storing data in an integrated circuit is also described.

公开(公告)号：US10263623B1

公开(公告)日：2019-04-16

申请号：US16107751

申请日：2018-08-21

Applicant: Xilinx, Inc.

Inventor： Yanran Chen ,  Pierre Maillard ,  Michael J. Hart

IPC: G11C17/18 ,  H03K19/173 ,  H03K17/00 ,  G11C11/412 ,  H03K19/003

Abstract: A circuit for storing data in an integrated circuit is described. The circuit comprises an inverter comprising a first transistor having a first gate configured to receive input data and a first output configured to generate a first inverted data output and a second transistor having a second gate configured to receive the input data and a second output configured to generate a second inverted data output; a first pass gate coupled to the first output of the inverter; a second pass gate coupled to the second output of the inverter; and a storage element having an input coupled to receive an output of the first pass gate and an output of the second pass gate. A method of storing data in an integrated circuit is also described.

公开(公告)号：US10958067B2

公开(公告)日：2021-03-23

申请号：US16136104

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Pierre Maillard ,  Yanran Chen ,  Michael J. Hart

IPC: H02H9/04 ,  H03K17/693 ,  H02H5/00

Abstract: An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contact pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

公开(公告)号：US11428733B1

公开(公告)日：2022-08-30

申请号：US17339223

申请日：2021-06-04

Applicant: XILINX, INC.

Inventor： Yanran Chen ,  Edward C. Priest ,  Martin L. Voogel ,  Hing Yan To

IPC: G01R31/28

Abstract: Some examples described herein provide for an on-die virtual probe in an integrated circuit structure for measurement of voltages. In an example, an integrated circuit comprises a voltage-controlled frequency oscillator circuitry and a processor circuitry. The voltage-controlled frequency oscillator circuitry comprises a plurality of circuitry components and is configured to generate a signal having a frequency related to a supply voltage. The voltage-controlled frequency oscillator circuitry is disposed at a location of the integrated circuit proximal to the supply voltage being monitored. The processor circuitry is configured to identify a relationship between the frequency of the signal and the supply voltage. The processor circuitry is also configured to determine a value of the supply voltage associated with the signal based on the identified relationship. The processor circuitry further monitors on-die transient voltages at the location of the integrated circuit based on the value of the supply voltage.

公开(公告)号：US20200091713A1

公开(公告)日：2020-03-19

申请号：US16136104

申请日：2018-09-19

Applicant: Xilinx, Inc.

Inventor： Pierre Maillard ,  Yanran Chen ,  Michael J. Hart

IPC: H02H9/04 ,  H03K17/693

Abstract: An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contract pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.