公开(公告)号：US07235490B2

公开(公告)日：2007-06-26

申请号：US10788216

申请日：2004-02-27

申请人： Yasuhiko Sato ,  Seiji Nakagawa ,  Jun Idebuchi ,  Motoya Kishida ,  Shuichi Taniguchi ,  Tsuyoshi Shibata

发明人： Yasuhiko Sato ,  Seiji Nakagawa ,  Jun Idebuchi ,  Motoya Kishida ,  Shuichi Taniguchi ,  Tsuyoshi Shibata

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  G03F7/09 ,  H01L21/0332

摘要： A method of manufacturing a semiconductor device comprises preparing a working film to be processed, forming an adhesion improving region on the working film for increasing an adhesion between the working film and a mask material containing carbon, forming the mask material on the working film, forming a resist pattern on the mask material, the mask material having a higher etching resistance for the working film than the resist pattern, transferring the pattern of the resist pattern onto the mask material, and etching the working film by using the mask material as a mask.

摘要翻译： 一种制造半导体器件的方法包括：制备待加工的工作薄膜，在工作薄膜上形成粘合改善区域，以增加工作薄膜和含有碳的掩模材料之间的粘附力，在工作薄膜上形成掩模材料，形成 在掩模材料上的抗蚀剂图案，掩模材料对抗蚀剂图案具有比工作膜更高的耐蚀刻性，将抗蚀剂图案的图案转印到掩模材料上，并且通过使用掩模材料作为掩模来蚀刻工作膜 。

公开(公告)号：US20100181598A1

公开(公告)日：2010-07-22

申请号：US12648974

申请日：2009-12-29

申请人： Tsutomu SATO ,  Jun Idebuchi ,  Yoshihisa Arie

发明人： Tsutomu SATO ,  Jun Idebuchi ,  Yoshihisa Arie

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/3086 ,  H01L21/76232 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

摘要： Etch block layers having an etching rate smaller than that of a first semiconductor forming a semiconductor substrate are formed on the sidewalls of device isolation grooves by applying oblique ion implantation of Ox, N, or C to the semiconductor substrate including the first semiconductor. Embedded layers including a second semiconductor are selectively formed in recesses by epitaxial-growing the second semiconductor having a lattice constant larger than that of the first semiconductor in the recesses.

摘要翻译： 通过对包括第一半导体的半导体衬底进行斜离子注入，在器件隔离槽的侧壁上形成蚀刻速度小于形​​成半导体衬底的第一半导体的蚀刻速率的蚀刻阻挡层。 包括第二半导体的嵌入层通过在凹槽中外延生长具有大于第一半导体的晶格常数的晶格常数的第二半导体而选择性地形成在凹陷中。

公开(公告)号：US20060084224A1

公开(公告)日：2006-04-20

申请号：US11245177

申请日：2005-10-07

申请人： Shinya Watanabe ,  Jun Idebuchi

发明人： Shinya Watanabe ,  Jun Idebuchi

IPC分类号： H01L21/8242

CPC分类号： H01L27/10867 ,  H01L27/10829 ,  H01L29/66181

摘要： According to the present invention, there is provided a semiconductor devise comprising: a gate electrode formed via a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a source region and drain region formed in a surface portion of said semiconductor substrate on two sides of a channel region positioned below said gate electrode; a capacitor insulating film formed in the surface portion of said semiconductor substrate to cover an inner surface near a bottom portion of a trench formed adjacent to one of said source region and drain region; a capacitor electrode formed to be buried in said trench covered with said capacitor insulating film; an insulating film formed to cover an inner surface of said trench, which is not covered with said capacitor insulating film; a conductive layer containing a predetermined impurity and formed in said trench so as to be buried in a portion covered with said insulating film on said capacitor electrode; a surface connecting layer formed on the surface of said semiconductor substrate to electrically connect said conductive layer and one of said source region and drain region; and an impurity diffusion inhibiting film formed to cover the inner surface of said trench to a predetermined depth from an interface between said surface connecting layer and conductive layer, and having a film thickness smaller than that of said insulating film.

摘要翻译： 根据本发明，提供了一种半导体器件，包括：栅电极，其经由选择性地形成在半导体衬底的预定区域上的栅极绝缘膜形成; 源极区域和漏极区域，形成在位于所述栅极电极下方的沟道区域的两侧的所述半导体衬底的表面部分中; 形成在所述半导体衬底的表面部分中以覆盖邻近所述源极区和漏极区之一形成的沟槽的底部附近的内表面的电容器绝缘膜; 电容器电极，被形成为埋在所述沟槽中，覆盖有所述电容器绝缘膜; 绝缘膜，形成为覆盖所述沟槽的内表面，其未被所述电容器绝缘膜覆盖; 包含预定杂质的导电层，形成在所述沟槽中，以埋在所述电容器电极上覆盖有所述绝缘膜的部分; 表面连接层，形成在所述半导体衬底的表面上，以将所述导电层与所述源极区和漏极区中的一个电连接; 以及形成为从所述表面连接层和导电层之间的界面覆盖所述沟槽的内表面至预定深度并且具有比所述绝缘膜的膜厚小的膜厚的杂质扩散抑制膜。