公开(公告)号：US3968328A

公开(公告)日：1976-07-06

申请号：US533773

申请日：1974-12-18

申请人： Yoshikazu Tsuchiya ,  Takenori Sonoda ,  Jun Takayama

发明人： Yoshikazu Tsuchiya ,  Takenori Sonoda ,  Jun Takayama

IPC分类号： H03M5/14 ,  G11B20/10 ,  G11B20/14 ,  H04L7/027 ,  H04L25/49 ,  H04L25/40

CPC分类号： H04L7/027

摘要： In dynamic modulation (D.M.) of non-return-to-zero pulse signals, the only condition under which the D.M. signal would remain in the same state, either 1 or 0, for two consecutive pulse intervals is when the NRZ signal includes the sequence 101. Two sampling signals at the proper clock repetition rate are generated from the D.M. signal by the decoder and are successively used to sample the D.M. signal and to sample the signal resulting from the first sampling. Information of the state of the D.M. signal at the time of the first sampling is retained to be compared with the state of the D.M. signal at a later time, and the state of one of the compared signals is separately compared with the state of a signal between the first-compared signals. If the wrong clock pulses midway between the correct clock pulses are used in making the comparisons, a correction signal will be generated in the last half of the second consecutive pulse interval in which the D.M. signal remains in the same state. This correction signal is used to adjust the clock pulse selector to select the correct pulses.

摘要翻译： 在非归零脉冲信号的动态调制（D.M.）中，唯一的条件是D.M. 当NRZ信号包括序列101时，对于两个连续的脉冲间隔，信号将保持在相同的状态，无论是1还是0。两个采样信号以适当的时钟重复率从D.M生成。 信号由解码器连续用于采样D.M. 信号并采样从第一次采样得到的信号。 信息状态的D.M. 保持第一采样时的信号与D.M的状态进行比较。 信号，并且一个比较信号的状态与第一比较信号之间的信号的状态分开比较。 如果在进行比较时使用正确的时钟脉冲之间的错误的时钟脉冲，则在第二个连续脉冲间隔的最后一半中将产生校正信号，其中D.M. 信号保持在相同的状态。 该校正信号用于调整时钟脉冲选择器以选择正确的脉冲。

公开(公告)号：US4348699A

公开(公告)日：1982-09-07

申请号：US149299

申请日：1980-05-13

申请人： Yoshikazu Tsuchiya ,  Masato Tanaka ,  Takenori Sonoda ,  Tetsu Watanabe ,  Chiaki Kanai ,  Nobuhiko Watanabe

发明人： Yoshikazu Tsuchiya ,  Masato Tanaka ,  Takenori Sonoda ,  Tetsu Watanabe ,  Chiaki Kanai ,  Nobuhiko Watanabe

IPC分类号： G11B27/02 ,  G11B5/09 ,  G11B15/52 ,  G11B20/10 ,  G11B27/32 ,  G11B5/00

CPC分类号： G11B15/52 ,  G11B20/10527 ,  G11B27/322

摘要： An apparatus for recording and/or reproducing a serial digitized analog signal controls the transport speed of a recording medium according to the sampling rate employed in digitizing the analog signal to produce a constant data density on the recording medium regardless of the sampling rate selected. The frequency of a fundamental clock signal establishes the sampling frequency during recording. A coded timing signal also recorded on the recording medium includes both a sync signal and a coded identity of the sampling frequency in use. During reproduction, the coded identity of the sampling frequency is used to select the same fundamental clock signal as was used during recording and the reproduced sync signal is phase compared with a reference signal derived from the fundamental clock signal to correspondingly control the speed and phase of transport of the recording medium. The fundamental clock signal may be manually varied during reproduction for pitch control of the reproduced analog signal.

摘要翻译： 用于记录和/或再现串行数字化模拟信号的装置根据在数字化模拟信号中采用的采样率来控制记录介质的传输速度，以在记录介质上产生恒定的数据密度，而不管选择的采样率如何。 基本时钟信号的频率在记录期间建立采样频率。 也记录在记录介质上的编码定时信号包括同步信号和使用中的采样频率的编码标识。 在再现期间，使用采样频率的编码标识来选择与记录期间相同的基本时钟信号，并且再现的同步信号与从基本时钟信号导出的参考信号进行相位比较，以相应地控制速度和相位 运输记录介质。 可以在再现期间手动地改变基本时钟信号以用于再现的模拟信号的音调控制。

公开(公告)号：US3981006A

公开(公告)日：1976-09-14

申请号：US481806

申请日：1974-06-21

申请人： Jun Takayama ,  Takenori Sonoda ,  Shoichi Nakamura

发明人： Jun Takayama ,  Takenori Sonoda ,  Shoichi Nakamura

IPC分类号： H03M1/18 ,  H03M1/00 ,  H03K13/02

CPC分类号： H03M1/124

摘要： An amplitude adjustment circuit transmits an analog signal to an analog-to-digital converter. If the resulting digital signal reaches the maximum permissible digital value, a monostable control circuit is triggered to cause the amplitude adjustment circuit to reduce the level of the analog signal a certain amount. If the digital signal again reaches the maximum permissible digital value before the control circuit returns to its stable condition a second monostable circuit is triggered (and the first one is retriggered) to cause the amplitude adjustment circuit to reduce the level of the analog signal another amount. The unstable interval for the second monostable circuit is shorter than for the first, and, in the absence of further triggering, both such circuits return to their stable states in succession. The digital signals are used to reconstruct the analog signal in apparatus similar to the encoding apparatus and including amplitude adjustment apparatus controlled by the amplitude compression signals.

摘要翻译： 幅度调整电路将模拟信号发送到模数转换器。 如果产生的数字信号达到最大允许数字值，则触发单稳态控制电路，使振幅调整电路将模拟信号的电平降低一定量。 如果数字信号在控制电路恢复到稳定状态之前再次达到最大允许数字值，则触发第二单稳态电路（并且第一个被重新触发），以使振幅调整电路将模拟信号的电平降低另一个量 。 第二单稳态电路的不稳定间隔比第一单稳态电路短，并且在没有进一步触发的情况下，这两个电路都连续返回到它们的稳定状态。 数字信号用于重构与编码装置类似的装置中的模拟信号，并且包括由幅度压缩信号控制的幅度调节装置。

公开(公告)号：US3981005A

公开(公告)日：1976-09-14

申请号：US481804

申请日：1974-06-21

申请人： Jun Takayama ,  Takenori Sonoda

发明人： Jun Takayama ,  Takenori Sonoda

IPC分类号： H03M1/18 ,  H03M1/00 ,  H03M1/70 ,  H04B14/04 ,  H03K13/02

CPC分类号： H03M1/124

摘要： A signal conversion system in which an analog signal of a certain magnitude can be encoded as a digital signal making full use of the available number of bits of an A/D converter. The system includes amplitude adjustment apparatus with an up-down counter actuated by the maximum available binary value of the digital signal to count UP one step and set an amplitude selection circuit to effectively attenuate the amplitude of the analog signal by a predetermined amount. The counter may have more than one memorizable count level to control a corresponding number of amplitude selection levels. The counter counts DOWN when the most significant bit of the digital signal drops from 1 to 0. The invention includes a corresponding analog signal reconstruction circuit except that it includes a D/A converter that produces an analog signal at maximum value that must be attenuated for low-amplitude values.

摘要翻译： 一种信号转换系统，其中可以将一定幅度的模拟信号编码为充分利用A / D转换器的可用位数的数字信号。 该系统包括具有由数字信号的最大可用二进制值启动的升降计数器的幅度调节装置，以计数一步，并设置幅度选择电路以有效地将模拟信号的振幅衰减预定量。 计数器可以具有多于一个可记忆的计数电平以控制对应数量的幅度选择电平。 当数字信号的最高有效位从1下降到0时，计数器将向下计数。本发明包括相应的模拟信号重构电路，除了它包括D / A转换器，其产生必须衰减的最大值的模拟信号， 低振幅值。

公开(公告)号：US4520407A

公开(公告)日：1985-05-28

申请号：US465464

申请日：1983-02-10

申请人： Masato Tanaka ,  Takenori Sonoda

发明人： Masato Tanaka ,  Takenori Sonoda

IPC分类号： G11B27/02 ,  G11B20/10 ,  G11B20/12 ,  G11B27/032 ,  G11B27/036 ,  G11B27/038 ,  G11B5/00

CPC分类号： G11B27/032 ,  G11B20/10527 ,  G11B27/036 ,  G11B27/038 ,  G11B2020/10592 ,  G11B2220/90 ,  G11B2220/913

摘要： An apparatus for recording and/or reproducing a digital signal made up of a plurality of channel signals digitally recorded in respective tracks on a magnetic record medium comprises a reproducing circuit which reproduces the channel signals recorded in the respective tracks, a recording circuit associated with the tracks which records digital signals in the tracks, and a selector circuit which selectively supplies the reproduced channel signals to the recording circuit for digital recording by the latter in at least a selected one of the tracks on the magnetic record medium.

摘要翻译： 一种用于记录和/或再现由数字记录在磁记录介质上的相应磁道中的多个通道信号组成的数字信号的装置包括再现记录在各个磁道中的通道信号的再现电路，与该磁记录介质相关联的记录电路 在轨道中记录数字信号的轨道，以及选择器电路，其选择性地将再现的频道信号提供给记录电路，用于通过磁记录介质中的至少一个轨道中的至少一个磁道进行数字记录。

公开(公告)号：US4402021A

公开(公告)日：1983-08-30

申请号：US290196

申请日：1981-08-05

申请人： Takenori Sonoda ,  Nobuhiko Watanabe ,  Masato Tanaka

发明人： Takenori Sonoda ,  Nobuhiko Watanabe ,  Masato Tanaka

IPC分类号： G11B27/02 ,  G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/10 ,  G11B27/28 ,  G11B27/32 ,  G11B15/18

CPC分类号： G11B20/10527 ,  G11B20/1204 ,  G11B20/1809 ,  G11B27/107 ,  G11B27/322 ,  G11B27/323 ,  G11B20/1202 ,  G11B2020/10546 ,  G11B2220/90 ,  G11B2220/913

摘要： At least one channel of digitized information is recorded in at least one data track on a record medium by forming data blocks, each containing a predetermined number of data words representing the digitized information, and recording successive data blocks in at least one data track. A block address also is generated to identify each of the respective data blocks, this block address also being recorded with the data block in the data track. A predetermined number of successive data blocks is recorded in the data track in a sector interval. A control signal having at least a sector address for identifying the sector interval also is generated, and this control signal is recorded in a separate control track, successive control signals being recorded in successive sector intervals. The least significant bit of the sector address is coincident with the most significant bit of the block address, such that the block address is repeated with a periodicity related to the sector interval. The combination of the sector and block addresses is used to access a desired one of the recorded data blocks.

摘要翻译： 数字化信息的至少一个通道通过形成数据块而被记录在记录介质上的至少一个数据轨道中，每个数据块包含表示数字化信息的预定数量的数据字，并将连续数据块记录在至少一个数据轨道中。 生成块地址以识别每个相应的数据块，该块地址也与数据轨道中的数据块一起记录。 预定数量的连续数据块以扇区间隔被记录在数据轨道中。 至少具有用于识别扇区间隔的扇区地址的控制信号也被产生，并且该控制信号被记录在单独的控制轨道中，连续的控制信号以连续的扇区间隔被记录。 扇区地址的最低有效位与块地址的最高有效位一致，使得以与扇区间隔相关的周期重复块地址。 扇区和块地址的组合用于访问所需的一个记录的数据块。

公开(公告)号：US4429390A

公开(公告)日：1984-01-31

申请号：US290848

申请日：1981-08-07

申请人： Takenori Sonoda ,  Nobuhiko Watanabe ,  Masato Tanaka

发明人： Takenori Sonoda ,  Nobuhiko Watanabe ,  Masato Tanaka

IPC分类号： H03M13/00 ,  G08C19/28 ,  G11B5/09 ,  G11B20/12 ,  G11B20/18 ,  H03M13/27 ,  G06F11/10

CPC分类号： G11B20/1809

摘要： A digital signal is encoded for error correction, and the encoded digital signal is transmitted in M transmitting paths. The signal to be encoded occurs as N sequences of data words. A plurality n of sequences of error correcting words are generated from respective words of the N sequences delayed by respective different delay times of (D-di) words, where d.sub.i is a whole number associated with an ith one of the n error correcting word sequences. The resulting N data word sequences and n error correcting word sequences are provided with respective different total delay times, so that the total delays of the N sequences differ by an integral number D of words from one another. Blocks of the delayed N data sequences and n error correcting word sequences are formed and the blocks are cyclically distributed among the M transmitting paths. The values of M, N, n, D, and d.sub.i are selected so that the least common multiple of any two values of (d-d.sub.i) is greater than (N+n-1)D; and for any value of (D-di), (d-di) and M are relatively prime. Favorably, M is selected as 2.sup. k, and (D-d.sub.i) is odd.

摘要翻译： 数字信号被编码用于纠错，并且编码的数字信号在M个发送路径中发送。 待编码的信号以数据字的N个序列发生。 从（D-di）个字的不同延迟时间延迟的N个序列的各个字生成多个n个纠错字序列，其中di是与n个纠错字序列中的第i个相关联的整数 。 所得到的N个数据字序列和n个纠错字序列被提供有相应不同的总延迟时间，使得N个序列的总延迟彼此相差一个单词的整数D。 形成延迟的N个数据序列的块和n个纠错字序列，并且这些块在M个发送路径之间循环地分布。 选择M，N，n，D和di的值，使得（d-di）任意两个值的最小公倍数大于（N + n-1）D; 并且对于（D-di），（d-di）和M的任何值都是相同的。 有利地，选择M为2k，（D-di）为奇数。

公开(公告)号：US5537537A

公开(公告)日：1996-07-16

申请号：US507780

申请日：1995-07-26

申请人： Daisuke Fujikawa ,  Takenori Sonoda ,  Kenichi Sakai

发明人： Daisuke Fujikawa ,  Takenori Sonoda ,  Kenichi Sakai

IPC分类号： G11B5/00 ,  G11B5/012 ,  G11B19/00 ,  G11B19/02 ,  G11B19/12 ,  G11B20/10 ,  G11B20/18 ,  G06F11/34

CPC分类号： G11B5/012 ,  G11B19/00 ,  G11B19/02 ,  G11B19/12 ,  G11B20/1816

摘要： A hard disc drive includes a self-diagnostic program which is stored either in ROM, on the magnetic disc or the like. This program enables the disc drive to be placed in an environment wherein a predetermined temperature is maintained and a so called "burn in" diagnostic carried out without the need for host computers and interface cabling. The outcome of the diagnostic can be recorded on a suitable media within the drive for later accessing.

摘要翻译： 硬盘驱动器包括存储在ROM中，磁盘上等的自诊断程序。 该程序使得磁盘驱动器能够被放置在保持预定温度并进行所谓的“刻录”诊断而不需要主计算机和接口布线的环境中。 诊断结果可以记录在驱动器内的合适的介质上，以供以后访问。

公开(公告)号：US4441184A

公开(公告)日：1984-04-03

申请号：US290850

申请日：1981-08-07

申请人： Takenori Sonoda ,  Nobuhiko Watanabe ,  Masato Tanaka

发明人： Takenori Sonoda ,  Nobuhiko Watanabe ,  Masato Tanaka

IPC分类号： G11B20/12 ,  G08C19/28 ,  G11B20/18 ,  H03M13/27 ,  H04B7/17 ,  H04B14/04 ,  H04B15/00 ,  G06F11/10

CPC分类号： G11B20/1809 ,  G11B20/1876

摘要： A PCM digital signal is provided with double-interleaving and error-correction encoding to protect against errors occurring during transmission, which can be carried out by magnetic recording and reproducing. The PCM signal is processed as error correcting blocks of several data word sequences and an associated error correction word sequence, and the double-interleaved sequences are then transmitted as transmission blocks. Up to one erroneous word in each error correction block can be corrected by using the error correction word sequence. Any uncorrectable word can be compensated by substituting a synthetic word interpolated from immediately preceding and following data words known to be correct. The distance between successive data words is made as great as possible so that a long burst error is unlikely to affect the ability to compensate uncorrectable errors. To achieve this, alternate words of the PCM signal are distributed to odd and even groups of sequences, and the interleaving is carried out by imparting different delay times to the respective sequences such that the greatest delay time imparted to the odd sequences is less than the shortest delay time imparted to the even sequences. The error correction word sequence is provided with a delay time intermediate the greatest delay time of the odd sequences and the shortest delay time of the even sequences.

摘要翻译： PCM数字信号具有双交错和纠错编码，以防止在传输期间发生的错误，这可以通过磁记录和再现来执行。 PCM信号被处理为几个数据字序列和相关联的纠错字序列的纠错块，然后将双交错序列作为传输块传输。 可以通过使用纠错字序列来校正每个纠错块中的一个错误字。 任何不可校正的单词都可以通过替换从已知正确的前一个和后续数据字内插的合成词来进行补偿。 连续数据字之间的距离尽可能大，使得长突发错误不太可能影响补偿不可校正错误的能力。 为了实现这一点，PCM信号的交替字被分配给奇数和偶数序列，并且通过给各个序列赋予不同的延迟时间来执行交织，使得赋予奇数序列的最大延迟时间小于 给予偶数序列的最短延迟时间。 误差校正字序列具有在奇数序列的最大延迟时间和偶数序列的最短延迟时间之间的延迟时间。

公开(公告)号：US4389681A

公开(公告)日：1983-06-21

申请号：US286963

申请日：1981-07-27

申请人： Masato Tanaka ,  Takenori Sonoda ,  Nobuhiko Watanabe

发明人： Masato Tanaka ,  Takenori Sonoda ,  Nobuhiko Watanabe

IPC分类号： G11B5/09 ,  G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  G11B27/10 ,  G11B5/02

CPC分类号： G11B27/107 ,  G11B20/10527 ,  G11B20/1204 ,  G11B20/1806 ,  G11B20/1202 ,  G11B2020/10546 ,  G11B2020/1087 ,  G11B2220/90

摘要： At least one channel of digitized information is recorded in a selected number of data tracks by a record medium. The digitized information is encoded, modulated and then recorded in a predetermined number of tracks. For example, if n channels of digitized information are to be recorded in m data tracks, then each channel is recorded in m/n data tracks (m.gtoreq.n). A control signal is generated to include control data representing at least one of the following: (a) the number of data tracks in which each channel of digitized information is recorded, (b) the encoding scheme used to encode the information, (c) the type of modulation used to modulate the encoded information and (d) the relative speed of movement of the record medium. The control signal is recorded in a separate control track. Thus, the control signal represents the particular format in which the digitized information is recorded.

摘要翻译： 数字化信息的至少一个通道由记录介质记录在选定数量的数据轨道中。 数字化信息被编码，调制，然后记录在预定数量的磁道中。 例如，如果n个通道的数字化信息要记录在m个数据轨道中，则每个通道被记录在m / n个数据轨道（m> / = n）中。 生成控制信号以包括表示以下至少一个的控制数据：（a）记录数字化信息的每个通道的数据轨道的数量，（b）用于编码信息的编码方案，（c） 用于调制编码信息的调制类型和（d）记录介质的相对移动速度。 控制信号记录在单独的控制轨道中。 因此，控制信号表示记录数字化信息的特定格式。