公开(公告)号：USRE43085E1

公开(公告)日：2012-01-10

申请号：US11404125

申请日：2006-04-13

申请人： Tao Lin ,  Tianhua Tang

发明人： Tao Lin ,  Tianhua Tang

IPC分类号： H04N9/73

CPC分类号： H04N9/735

摘要： An adaptive color enhancer applies different scale factors to different pixels in a digital image. More color enhancement occurs for bright pixels and for dim pixels than for average-intensity pixels. Also, more color enhancement is applied to the more colorful pixels while less color enhancement is applied to dull, less-colorful pixels. Rather than enhance all pixels to the same extent, the bright, colorful pixels are enhanced further than the average. Likewise, dim areas are color enhanced more than average. A calculation unit receives a YUV pixel. The Y value is compared to range limits and a piece-wise-linear (PWL) function generates an intermediate scale factor. The absolute values of the U and V color values are combined to create a colorfulness factor. The colorfulness factor is also used with a PWL function and the intermediate scale factor to generate a final scale factor for that pixel. The final scale factor is then multiplied by the U and V values of the pixel to generate a color-corrected pixel.

摘要翻译： 自适应颜色增强器对数字图像中的不同像素应用不同的比例因子。 对于亮像素和暗像素，对于平均亮度像素，会发生更多的颜色增强。 此外，更多的颜色增强被应用于更多彩色的像素，而较少的颜色增强被应用于暗淡的，不太多彩的像素。 而不是以相同的程度增强所有像素，明亮，彩色的像素比平均值进一步增强。 同样，昏暗的地区比平均色彩增强。 计算单元接收YUV像素。 将Y值与范围限制进行比较，并且分段线性（PWL）函数生成中间缩放因子。 U和V颜色值的绝对值被组合以产生色彩因子。 色彩因子也与PWL功能和中等比例因子一起使用，以生成该像素的最终比例因子。 然后将最终比例因子乘以像素的U和V值以产生经色彩校正的像素。

公开(公告)号：USRE43235E1

公开(公告)日：2012-03-13

申请号：US12789856

申请日：2010-05-28

申请人： Takatoshi Ishii ,  Edmund Cheung ,  Sherwood Brannon

发明人： Takatoshi Ishii ,  Edmund Cheung ,  Sherwood Brannon

IPC分类号： G06F12/10 ,  G06F12/06 ,  G09G3/37 ,  G09G5/00 ,  G09G5/36

CPC分类号： G09G5/39 ,  G09G5/14 ,  G09G5/363 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/021

摘要： A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data, .eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

摘要翻译： 与电池供电设备一起使用的片上系统（SOC）图形控制器允许降低功耗的显示模式。 微处理器写入作为虚拟存储器中单个连续地址块的帧缓冲器。 存储器管理单元（MMU）将帧缓冲器地址转换为多个物理块。 图形控制器从多个物理块中获取像素，包括片上存储器中的块和外部存储器中的块。 在低功耗模式下，像素只能从较低功耗的片上存储器中取出，而不是较高功率的外部存储器。 定义一个较小的显示窗口，窗口外的像素将被虚拟数据替代，从而消除外部存储器提取。 较小的显示窗口落在片内存储器的第一个块内。 在待机模式下，状态和其他信息可以显示在较小的显示窗口中，全屏显示全功能模式。

公开(公告)号：USRE43357E1

公开(公告)日：2012-05-08

申请号：US11241903

申请日：2005-09-30

申请人： Tao Lin

发明人： Tao Lin

IPC分类号： H04N5/208 ,  G06K9/40

CPC分类号： G06T3/4007 ,  G06T3/4015 ,  G06T3/403 ,  G06T5/003 ,  G06T7/13 ,  G06T2207/10024 ,  G06T2207/20192 ,  H04N9/045

摘要： A digital-camera processor receives a stream of mono-color pixels in a Bayer pattern from a sensor. Two lines of the pattern are stored in a 2-line buffer. Red, Blue, and Green interpolators receive a 3×3 array of pixels from the 2-line buffer. The interpolators generate missing color values by interpolation. For green, horizontal interpolation is performed for odd lines, while vertical interpolation is performed for even lines. Horizontal and vertical interpolation is thus alternated with alternate lines. Edge detection is performed at the same time as interpolation, on the green pixels from the 2-line buffer. An edge-detection filter is multiplied by the green pixels in the 3×3 array from the 2-line buffer. Different edge-detection filters are used for odd and even lines. These filters are modified to detect edges running perpendicular to the direction of the green interpolation filter. Edges in the same direction as the interpolation filter are ignored. Thus blurring caused by the green interpolation does not affect edge detection. The result of the edge-detection filter is compared to two different threshold values, one for green and one for red and blue. When an edge is detected, an edge enhancer is activated. The edge enhancer adds a scaled factor to the interpolated R, G, or B values to sharpen the detected edge. The line buffer stores only 2 full lines of pixels and no full-frame buffer is needed.

摘要翻译： 数码相机处理器从传感器接收拜耳图案中的单色像素流。 两行图案存储在2行缓冲区中。 红色，蓝色和绿色插值器从2行缓冲区接收3×3像素阵列。 插值器通过插值生成缺失的颜色值。 对于绿色，对于奇数行执行水平插补，而对于偶数行执行垂直内插。 水平和垂直插补因此与交替线交替。 边缘检测与内插同时执行，来自2行缓冲区的绿色像素。 边缘检测滤波器乘以2线缓冲器中3×3阵列中的绿色像素。 不同的边缘检测滤波器用于奇数和偶数行。 这些滤波器被修改以检测垂直于绿色插值滤波器的方向运行的边缘。 与内插滤波器相同方向的边缘被忽略。 因此，由绿色插补引起的模糊不会影响边缘检测。 将边缘检测滤波器的结果与两个不同的阈值进行比较，一个用于绿色，一个用于红色和蓝色。 当检测到边缘时，边缘增强器被激活。 边缘增强器向内插的R，G或B值添加缩放因子以锐化检测到的边缘。 行缓冲区仅存储2行全部像素，并且不需要全帧缓冲区。

公开(公告)号：USRE42555E1

公开(公告)日：2011-07-19

申请号：US11267917

申请日：2005-11-04

申请人： Tao Lin ,  Vincent Chor-Fung Yu ,  Tianhua Tang ,  Beong-Kwon Hwang

发明人： Tao Lin ,  Vincent Chor-Fung Yu ,  Tianhua Tang ,  Beong-Kwon Hwang

IPC分类号： H04N5/208

CPC分类号： G06T3/4015 ,  G06T3/4007 ,  G06T3/403 ,  H04N9/045

摘要： A digital-camera processor receives mono-color digital pixels from an image sensor. Each mono-color pixel is red, blue, or green. The stream of pixels from the sensor has alternating green and red pixels on odd lines, and blue and green pixels on even lines in a Bayer pattern. Each mono-color pixel is white balanced by multiplying with a gain determined in a previous frame and then stored in a line buffer. A horizontal interpolator receives an array of pixels from the line buffer. The horizontal interpolator generates missing color values by interpolation within horizontal lines in the array. The intermediate results from the horizontal interpolator are stored in a column buffer, and represent one column of pixels from the line buffer. A vertical interpolator generates the final RGB value for the pixel in the middle of the column register by vertical interpolation. The RGB values are converted to YUV. The vertical interpolator also generates green values for pixels above and below the middle pixel. These green values are sent to an edge detector. The edge detector applies a filter to the 3 green values and 6 more green values from the last 2 clock cycles. When an edge is detected, an edge enhancer is activated. The edge enhancer adds a scaled factor to the Y component to sharpen the detected edge. Color enhancement is performed on the U and V components. The line buffer stores only 4 full lines of pixels and no full-frame buffer is needed.

摘要翻译： 数码相机处理器从图像传感器接收单色数字像素。 每个单色像素是红色，蓝色或绿色。 来自传感器的像素流在奇数行上具有交替的绿色和红色像素，并且在拜耳图案中的偶数行上的蓝色和绿色像素。 每个单色像素通过与前一帧中确定的增益相乘然后存储在行缓冲器中来进行白平衡。 水平内插器从行缓冲器接收像素阵列。 水平内插器通过在数组中的水平线内的插值生成缺失的颜色值。 来自水平插值器的中间结果存储在列缓冲器中，并且表示来自行缓冲器的一列像素。 垂直内插器通过垂直内插生成列寄存器中间的像素的最终RGB值。 RGB值被转换为YUV。 垂直内插器还为中间像素上方和下方的像素生成绿色值。 这些绿色值被发送到边缘检测器。 边缘检测器对最近2个时钟周期的3个绿色值和6个绿色值应用滤波器。 当检测到边缘时，边缘增强器被激活。 边缘增强器向Y分量添加缩放因子以锐化检测到的边缘。 对U和V分量执行色彩增强。 行缓冲区仅存储4行全像素，不需要全帧缓冲区。

公开(公告)号：USRE39963E1

公开(公告)日：2007-12-25

申请号：US11129758

申请日：2005-05-13

申请人： Edmund Cheung ,  Otto Sponring

发明人： Edmund Cheung ,  Otto Sponring

IPC分类号： G06F1/32

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14

摘要： An application specific integrated circuit (ASIC) has a clock controller that dynamically selects an appropriate clock frequency for a resource. The ASIC includes a central processing unit (CPU), on-chip memory, a memory controller controlling external memory devices, a system bus, and various peripheral controllers. Devices that can be accessed by other devices, such as the on-chip memory, the memory controller, and the system bus are “resources.” The devices that access the resources are “controllers.” The ASIC generates a master clock and the clock controller derives clocks for driving the resources and controllers from the master clock. A multiplexer (MUX) in the clock controller selects the clock that is passed to a resource. Each controller has a request line to the clock controller for signaling when the controller is accessing a resource. The clock controller has a programmable register for each controller holding a value representing the bandwidth utilization of the controller and an adder and a frequency table. The adder sums the contents of the bandwidth registers of the controllers that are accessing a resource. The sum is an index to an entry in a frequency table. The value held in the frequency table is applied to the selection inputs of the MUX to select the clock for the resource. If no controllers are requesting access to the memory controller, the clock controller shuts down the memory clock. Accordingly, the clock frequency of the resource is determined by the bandwidth utilization of the controllers requesting access to the resource.

摘要翻译： 专用集成电路（ASIC）具有时钟控制器，其为资源动态地选择适当的时钟频率。 ASIC包括中央处理单元（CPU），片上存储器，控制外部存储器件的存储器控​​制器，系统总线和各种外围控制器。 其他设备可以访问的设备，如片上存储器，存储器控制器和系统总线都是“资源”。 访问资源的设备是“控制器”。 ASIC生成主时钟，时钟控制器从主时钟驱动资源和控制器的时钟。 时钟控制器中的多路复用器（MUX）选择传递给资源的时钟。 每个控制器具有到时钟控制器的请求线，用于在控制器正在访问资源时进行信令。 时钟控制器具有用于每个控制器的可编程寄存器，其具有表示控制器的带宽利用率的值，以及加法器和频率表。 加法器对正在访问资源的控制器的带宽寄存器的内容进行求和。 总和是频率表中条目的索引。 将频率表中保持的值应用于MUX的选择输入以选择资源的时钟。 如果没有控制器请求访问存储器控制器，则时钟控制器关闭存储器时钟。 因此，资源的时钟频率由请求访问资源的控制器的带宽利用率确定。

公开(公告)号：USRE39578E1

公开(公告)日：2007-04-17

申请号：US11176885

申请日：2005-07-07

申请人： Wei-Ping Lu

发明人： Wei-Ping Lu

IPC分类号： G06F7/508

CPC分类号： G06F7/5055 ,  G06F7/508 ,  G06F2207/3884

摘要： An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next count. All-ones detect logic detects when all lesser-significance bits in the current count are ones. When all lesser bits are ones, the sum logic toggles the count bit to generate the sum bit for that bit position. Pre-carry logic generates pre-carry lookahead signals from the sum bits. The pre-carry lookahead signals are latched into pipelined carry registers. The pipelined carry registers drive pipelined carry lookahead signals to the all-ones detect logic. Thus carry lookahead signals are generated from a prior sum but used in a next clock cycle to generate then next sum.

摘要翻译： 一个增量器管道进位先行信号的产生。 计数寄存器保存增量器的当前计数。 当前计数作为输入反馈到和逻辑，其产生作为下一个计数被锁存到计数寄存器中的和位。 全部检测逻辑检测当前计数中所有较低位的位是否为1。 当所有较小的位都为1时，总和逻辑切换计数位以产生该位位置的和位。 预进位逻辑从和位产生预进位前置信号。 预进位前置信号被锁存到流水线进位寄存器中。 流水线进位寄存器将流水线进位先行信号驱动到全指示检测逻辑。 因此，进位先行信号是从先前的和产生的，但是在下一个时钟周期中使用，以产生下一个和。