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    DIGITAL FILTER CIRCUIT
    1.
    发明申请
    DIGITAL FILTER CIRCUIT 审中-公开
    数字滤波电路

    公开(公告)号：US20150162896A1

    公开(公告)日：2015-06-11

    申请号：US14117547

    申请日：2012-04-19

    Applicant: Hidenori Kayama

    Inventor： Hidenori Kayama

    IPC: H03H17/02

    CPC classification number: H03H17/0283 ,  H03H17/06 ,  H03H2218/06 ,  H03H2218/08

    Abstract: A digital filter circuit that implements a filtering process for a plurality of channels having different sampling rates with a small circuit complexity includes a delay circuit divided into first to mth groups of delay devices, processing stage division means for selectively supplying first to (m−1)th input delayed signals and output signals of the second to mth taps to the first to (m−1)th groups of delay devices, tap coefficient supply means for supplying first to mth selected tap coefficients, a multiplying circuit for multiplying outputs of the first to mth taps and the first to mth selected tap coefficients, an adding circuit for adding up first to mth multiplication results, an accumulative addition part for accumulatively adding the first to mth multiplication results and addition results of the plurality of adders, and an output data format generation part for generating an output format of a filtering process result of each of processing stages from the plurality of accumulative addition results and outputs of the adding circuit.

    Abstract translation: 实现具有小电路复杂度的具有不同采样率的多个通道的滤波处理的数字滤波器电路包括分为第一至第m组延迟器件的延迟电路，用于选择性地先向（m-1 第二输入延迟信号和第二到第m组抽头的输出信号到第一至第（m-1）延迟装置组，用于提供第一至第m选择抽头系数的抽头系数提供装置， 第一到第m个抽头和第一个到第m个选择的抽头系数，一个用于将第一乘法相加到第m个乘法结果的加法电路，用于累积加上第一到第m乘法结果的加法部分和多个加法器的相加结果， 数据格式生成部，用于从多个累加生成各处理级的滤波处理结果的输出格式 加法电路的相加结果和输出。

    Generating filter coefficients for a multi-channel notch rejection filter
    2.
    发明授权
    Generating filter coefficients for a multi-channel notch rejection filter 有权
    为多通道陷波抑制滤波器生成滤波器系数

    公开(公告)号：US09002917B2

    公开(公告)日：2015-04-07

    申请号：US12847685

    申请日：2010-07-30

    Applicant: Hector Rubio ,  Garritt W. Foote

    Inventor： Hector Rubio ,  Garritt W. Foote

    IPC: G06F17/10 ,  H03H17/02

    CPC classification number: H03H17/025 ,  H03H17/0294 ,  H03H2017/0298 ,  H03H2218/06 ,  H03H2218/10

    Abstract: Provided is a system for generating coefficient values. The system may include a base function generator and a series of accumulators including a leading and a last accumulator. In the series of accumulators, the data output of each accumulator, except the last, may be coupled to the data input of a successive adjacent accumulator. The base function generator may be configured to output, to the leading accumulator, a series of data values that may correspond to a base function that is a specified order derivative of a filter function. Each accumulator may be configured to: add a data value currently at its data input to a currently stored data value to produce an updated data value that may correspond to a respective value of a specified order integral of the base function; store the updated data value in the accumulator; and output the updated data value at its data output.

    Abstract translation: 提供一种用于产生系数值的系统。 系统可以包括基本功能发生器和包括前导和最后一个累加器的一系列累加器。 在一系列累加器中，除了最后一个累加器之外，每个累加器的数据输出可以耦合到连续的相邻累加器的数据输入。 基本函数发生器可以被配置为向前导累加器输出可以对应于作为滤波器函数的指定阶导数的基函数的一系列数据值。 每个累加器可以被配置为：将当前在其数据输入处的数据值添加到当前存储的数据值以产生可以对应于基本函数的指定阶积分的相应值的更新数据值; 将更新的数据值存储在累加器中; 并在其数据输出端输出更新的数据值。

    Filter parallelization for high data throughput
    3.
    发明授权
    Filter parallelization for high data throughput 有权
    过滤并行化高数据吞吐量

    公开(公告)号：US08938483B1

    公开(公告)日：2015-01-20

    申请号：US13186868

    申请日：2011-07-20

    Applicant: Benjamin Egg ,  Frederic J. Harris ,  Christopher H. Dick

    Inventor： Benjamin Egg ,  Frederic J. Harris ,  Christopher H. Dick

    IPC: G06F17/10

    CPC classification number: H03H17/0223 ,  H03H17/06 ,  H03H2017/0247 ,  H03H2218/06

    Abstract: A filter can include a first channel and a second channel. The first channel can be configured to process a first term and a second term of an input vector using a first coefficient and a second coefficient of the filter. The first channel can be configured to generate a first term of an output vector. The second channel can be configured to process the first term and the second term of the input vector using the first coefficient and the second coefficient of the filter. The second channel can be configured to generate a second term of the output vector. The first and second channels can be configured to operate in parallel.

    Abstract translation: 滤波器可以包括第一通道和第二通道。 第一通道可以被配置为使用滤波器的第一系数和第二系数来处理输入向量的第一项和第二项。 可以将第一通道配置为生成输出向量的第一项。 第二通道可以被配置为使用滤波器的第一系数和第二系数来处理输入向量的第一项和第二项。 可以将第二通道配置为生成输出向量的第二项。 第一和第二通道可以被配置为并行操作。

    Multi-input IIR filter with error feedback
    4.
    发明授权
    Multi-input IIR filter with error feedback 有权
    具有错误反馈的多输入IIR滤波器

    公开(公告)号：US08645446B2

    公开(公告)日：2014-02-04

    申请号：US12952193

    申请日：2010-11-22

    Applicant: Maged F. Barsoum ,  Jinwen Xi ,  Dariush Dabiri

    Inventor： Maged F. Barsoum ,  Jinwen Xi ,  Dariush Dabiri

    IPC: G06F17/10

    CPC classification number: H03H17/04 ,  H03H2218/06

    Abstract: Methods and systems for multi-input IIR filters with error feedback are disclosed. By using multiple-inputs to generate multiple outputs during each iteration, a multi-input IIR filter in accordance with the present invention has greatly increased throughput. Furthermore, the addition of a multi-variable error feedback unit in accordance with the present invention in a multiple-input IIR filter can greatly increase the accuracy of the multi-variable IIR Filter.

    Abstract translation: 公开了具有误差反馈的多输入IIR滤波器的方法和系统。 通过在每次迭代期间通过使用多输入来产生多个输出，根据本发明的多输入IIR滤波器大大提高了吞吐量。 此外，在多输入IIR滤波器中添加根据本发明的多变量误差反馈单元可以大大提高多变量IIR滤波器的精度。

    High-frequency receiver with multiple-channel digital processing
    5.
    发明授权
    High-frequency receiver with multiple-channel digital processing 有权
    高频接收机采用多通道数字处理

    公开(公告)号：US08428532B2

    公开(公告)日：2013-04-23

    申请号：US12450773

    申请日：2008-04-10

    Applicant: Olivier Romain ,  Bruce Denby ,  Julien Denoulet

    Inventor： Olivier Romain ,  Bruce Denby ,  Julien Denoulet

    IPC: H04B1/06

    CPC classification number: G01S13/003 ,  G01S7/352 ,  G01S2007/356 ,  G01S2007/358 ,  H03H17/0685 ,  H03H2017/0214 ,  H03H2218/06

    Abstract: In the receive subsystem, the analogue-to-digital converter (40) works on the output of the low-noise amplifier (33), at a chosen rate (F), which corresponds to a bandwidth sampling. The processing stages comprise a custom circuit (5), with * an input memory (510) arranged to contain N successive digital samples, renewed at the chosen rate in blocks of M samples, * a complex digital low-pass filtering function (511, 512), of chosen cut-off frequency, operating on the input memory to supply N filtered digital samples (515), * an M-periodic summing function (531) on the N filtered digital samples, supplying M filtered and summed digital samples (533), * an M′M discrete Fourier transform stage (55), operating on these M filtered and summed digital samples, the digital signals on the M outputs (559) of the Fourier transform representing M separate channels, of width defined by the cut-off frequency of the abovementioned low-pass filter.

    Abstract translation: 在接收子系统中，模数转换器（40）以对应于带宽采样的选定速率（F）在低噪声放大器（33）的输出上工作。 处理阶段包括定制电路（5），其中输入存储器（510）被布置成包含N个连续的数字样本，以选定的速率以M个样本的块更新;复数数字低通滤波函数（511， 512），在输入存储器上工作以提供N个滤波的数字样本（515），* N个滤波的数字样本上的M周期求和函数（531），提供M个滤波和求和的数字样本（ 533），* M'M离散付里叶变换级（55），对这些M个滤波和求和的数字样本进行操作，表示M个分离信道的M个输出（559）上的数字信号，宽度由 上述低通滤波器的截止频率。

    HIGH-FREQUENCY RECEIVER WITH MULTIPLE-CHANNEL DIGITAL PROCESSING
    6.
    发明申请
    HIGH-FREQUENCY RECEIVER WITH MULTIPLE-CHANNEL DIGITAL PROCESSING 有权
    具有多通道数字处理的高频接收器

    公开(公告)号：US20100178894A1

    公开(公告)日：2010-07-15

    申请号：US12450773

    申请日：2008-04-10

    Applicant: Olivier Romain ,  Bruce Denby ,  Julien Denoulet

    Inventor： Olivier Romain ,  Bruce Denby ,  Julien Denoulet

    IPC: H04B1/16

    CPC classification number: G01S13/003 ,  G01S7/352 ,  G01S2007/356 ,  G01S2007/358 ,  H03H17/0685 ,  H03H2017/0214 ,  H03H2218/06

    Abstract: In the receive subsystem, the analogue-to-digital converter (40) works on the output of the low-noise amplifier (33), at a chosen rate (F), which corresponds to a bandwidth sampling. The processing stages comprise a custom circuit (5) with * an input memory (510) arranged to contain N successive digital samples, renewed at the chosen rate in blocks of M samples, * a complex digital low-pass filtering function (511, 512), of chosen cut-off frequency, operating on the input memory to supply N filtered digital samples, * an M-periodic summing function (531) on the N filtered digital samples, supplying M filtered and summed digital samples (533), * an M1M discrete Fourier transform stage (55), operating on these M filtered and summed digital samples, the digital signals on the M outputs (559) of the Fourier transform representing M separate channels, of width defined by the cut-off frequency of the abovementioned low-pass filter.

    Abstract translation: 在接收子系统中，模数转换器（40）以对应于带宽采样的选定速率（F）在低噪声放大器（33）的输出上工作。 处理阶段包括具有*输入存储器（510）的定制电路（5），输入存储器（510）被布置成包含N个连续的数字采样，以M个采样块中的选定速率更新;复数数字低通滤波函数（511,512 ），在输入存储器上操作以提供N个滤波的数字样本，*在N个滤波的数字样本上的M周期求和函数（531），提供M个滤波和求和的数字样本（533），* 在这些M个滤波和求和的数字样本上操作的M1M离散傅立叶变换级（55），表示M个分离通道的傅里叶变换的M个输出（559）上的数字信号，其宽度由 上述低通滤波器。

    CONTROL SYSTEM
    7.
    发明申请
    CONTROL SYSTEM 有权
    控制系统

    公开(公告)号：US20090271005A1

    公开(公告)日：2009-10-29

    申请号：US12429690

    申请日：2009-04-24

    Applicant: Knud Bank Christensen ,  Klas Ake Dalbjorn

    Inventor： Knud Bank Christensen ,  Klas Ake Dalbjorn

    IPC: G05B11/01 ,  G06F15/00

    CPC classification number: G10L21/00 ,  G10L2021/02166 ,  H03H17/06 ,  H03H2021/007 ,  H03H2218/06 ,  H04R3/005

    Abstract: A control system is provided for controlling a transducer array. The control system includes a plurality of sparse filters and integrators. The control system can be used to separate signals from a plurality of sources or to generate complex signal patterns that combine and map to different spatial regions.

    Abstract translation: 提供一种用于控制换能器阵列的控制系统。 控制系统包括多个稀疏滤波器和积分器。 控制系统可用于分离来自多个源的信号或者生成组合并映射到不同空间区域的复杂信号模式。

    Parallelized infinite impulse response (IIR) and integrator filters
    10.
    发明授权
    Parallelized infinite impulse response (IIR) and integrator filters 有权
    并联无限脉冲响应（IIR）和积分滤波器

    公开(公告)号：US07152084B2

    公开(公告)日：2006-12-19

    申请号：US10290484

    申请日：2002-11-08

    Applicant: François Gagnon ,  Claude Thibeault ,  Jean Belzile

    Inventor： François Gagnon ,  Claude Thibeault ,  Jean Belzile

    IPC: G06F17/10

    CPC classification number: H03H17/04 ,  H03H2017/0678 ,  H03H2218/06

    Abstract: A digital parallelized Infinite Impulse Response (IIR) integrator filter comprising a first channel having a first input and second channel having a second input, a first adder to add the two channel inputs, an integrator to integrate the added channel inputs to provide a first channel output is described herein. The second input channel is adjacent in time to the first channel input. The second channel further comprises a second adder which adds the first output with the second channel input in order to produce a second output, adjacent in time with the first output. This configuration can be generalized to n inputs and m outputs.

    Abstract translation: 一种数字并行无限脉冲响应（IIR）积分器滤波器，包括具有第一输入和第二通道的第一通道，具有第二输入;第一加法器，用于将两个通道输入相加;积分器，用于对所附加的通道输入进行积分，以提供第一通道 输出。 第二输入通道在时间上与第一通道输入相邻。 第二通道还包括第二加法器，该第二加法器将第一输出与第二通道输入相加以产生与第一输出在时间上相邻的第二输出。 该配置可以推广到n个输入和m个输出。

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