Abstract:
A stacked multiple electronic component interconnect structure includes a connector portion having a first and second connector surfaces. A first double sided land grid array having a first surface provided with a first plurality of connector units and a second surface provided with a second plurality of connector units, is positioned on the first connector surface. A second double sided land grid array having a first surface provided with a first plurality of connector units and a second surface provided with a second plurality of connector units is positioned on the second connector surface. A first electronic component is mounted to the second surface of the first land grid array and a second electronic component is mounted to the second surface of the second land grid array to form a stacked multiple electronic component interconnect structure that conserves space on an electronic board.
Abstract:
A method and an apparatus for managing power consumption of a server have been disclosed. In one embodiment, the method includes allowing a user to set a power management policy on a server, monitoring power consumption of a plurality of blades in the server, and automatically managing power consumption of the server in response to the power consumption of the plurality of blades based on the power management policy set by the user. Other embodiments have been claimed and described.
Abstract:
A method, apparatus and system for securely metering resource usage on a computing platform. Specifically, in one embodiment, various hardware metering counters on the device may provide a secure processing partition with usage information to enable the resources to be metered within the secure partition.
Abstract:
A highly dense form of static random-access memory (SRAM) takes advantage of transistor gates on both sides of silicon and high interconnectivity made possible by the complex form of silicon-on-insulator and three-dimensional integration. This technology allows one to form p-channel and n-channel devices very compactly by taking advantage of placement of gates on both sides, making common contacts and dense interconnections in 3D.
Abstract:
A system and method are provided for internet-based network topology discovery. A server in communication with a client, the server having a console having a managing device is provided to manage one or more network devices. A search engine is provided that is in communication with the managing device via a network including the Internet, the search engine capable of being accessed via the client. The console is used to formulate an Extensible Markup Language (XML) discovery information query, wherein the XML discovery information query is initiated automatically by the client. The console is further to send the XML discovery information query to the search engine to facilitate searching of discovery information relevant to the one or more network devices, wherein at least one of the one or more network devices includes an XML discovery information file, wherein at least one of the one or more network devices does not include the XML discovery information file. In response to sending the XML discovery information query, the console to receive one or more of the following via the search engine: first discovery information from the one or more network devices having the XML discovery information file, and second discovery information from a proxy device for the one or more network devices not including the XML discovery information files. The console is further used to generate a network topology map for the one or more network devices via the retrieved first and second discovery information.
Abstract:
A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device
Abstract:
A tamper resistant enclosure for an electronic circuit includes an inner copper case, a tamper sensing mesh wrapped around the inner case, an outer copper case enclosing the inner case and the tamper sensing mesh, and a venting device forming a vent channel from inside the inner case to outside the outer case, the vent channel passing between overlapping layers of the tamper sensing mesh and having at least one right angle bend along its length. The venting device includes two strips of a thin polyamide coverlay material laminated together along their length, and a length of wool yarn sandwiched between the two thin strips and extending from one end of the strips to the other end of the strips to form the vent channel. The length of yarn follows a zig-zag path between the first and second strips, the zig-zag path including at least one right angle bend.
Abstract:
An apparatus for controllably distorting the duty cycle of a clock signal is disclosed. Methods and systems using embodiments of the invention are also described.
Abstract:
A heat transfer apparatus comprises a thermally conductive member including a base having one or more surfaces adapted to absorb heat from an electronic component, and a mounting assembly including at least one mounting member directly coupled to the base and for direct attachment to the electronic component so that loading forces for mounting on it the electronic component are not directly applied to the base. The thermally conductive member is a graphite-based material. A compliant force applying mechanism is mounted generally on the base for controlling forces applied on the base.