公开(公告)号：US08379000B2

公开(公告)日：2013-02-19

申请号：US12453818

申请日：2009-05-22

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G5/00

CPC分类号： H03M1/661 ,  H03M1/68 ,  H03M1/76

摘要： A digital-to-analog converter, in which a plurality of reference voltages that differ from one another are grouped into first to (S+1)th reference voltage groups, includes a decoder and an amplifying circuit. The decoder includes: first to (S+1)th subdecoders for selecting respective ones of reference voltages corresponding to a value of a first bit group on an upper bit side of an input digital signal from the reference voltages of the first to (S+1)th reference voltage groups; and an (S+1)-input and 2-output type subdecoder for selecting and outputting two reference voltages out of reference voltages selected by the first to (S+1)th subdecoders, in accordance with a value of a second bit group on a lower side of the input digital signal. The amplifying circuit receives the two reference voltages as inputs and outputs a voltage level obtained by interpolation at a prescribed ratio.

摘要翻译： 将彼此不同的多个参考电压分组为第一至第（S + 1）个参考电压组的数模转换器包括解码器和放大电路。 解码器包括：第一到第（S + 1）个子编码器，用于选择对应于从第一至第（S + 1）个参考电压的输入数字信号的高位位上的第一位组的值的参考电压， 1）参考电压组; 和（S + 1）输入和2输出型子编码器，用于根据第二位组的值，选择并输出由第一至第（S + 1）个子解码器选择的参考电压中的两个参考电压 输入数字信号的下侧。 放大电路接收两个参考电压作为输入，并以规定的比例输出通过插值获得的电压电平。

公开(公告)号：US08274504B2

公开(公告)日：2012-09-25

申请号：US12385080

申请日：2009-03-30

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/0291

摘要： Disclosed is an output amplifier circuit including a differential stage, a first output stage that receives outputs of the differential stage, and a second output stage having an output thereof electrically connected to a load. The differential stage receives an input signal at a non-inverting input thereof. In the first connection configuration, an output of the first output stage is electrically disconnected from the output of the second output stage, outputs of the differential stage are electrically disconnected from inputs of the second output stage, and a second input of the differential stage is electrically connected to the output of the first output stage. In the second connection configuration, the output of the first output stage is electrically connected to the output of the second output stage, and the outputs of the differential stage is electrically connected to the inputs of the second output stage.

摘要翻译： 公开了一种输出放大器电路，其包括差分级，接收差分级的输出的第一输出级和具有电连接到负载的输出的第二输出级。 差分级在其非反相输入端接收输入信号。 在第一连接结构中，第一输出级的输出与第二输出级的输出电断开，差动级的输出与第二输出级的输入电断开，差动级的第二输入为 电连接到第一输出级的输出端。 在第二连接结构中，第一输出级的输出电连接到第二输出级的输出，差分级的输出电连接到第二输出级的输入。

公开(公告)号：US20120127138A1

公开(公告)日：2012-05-24

申请号：US13317858

申请日：2011-10-31

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G5/00 ,  H03F3/45

CPC分类号： G09G3/3677 ,  G09G3/3258 ,  G09G3/3291 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2330/021 ,  H03F1/0261 ,  H03F3/45179 ,  H03F3/4526 ,  H03F2200/18 ,  H03F2200/27 ,  H03F2203/45562 ,  H03F2203/45614 ,  H03F2203/45618 ,  H03F2203/45644 ,  H03F2203/45674 ,  H03F2203/45676 ,  H03F2203/45724 ,  H03F2203/45728

摘要： An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit, input and output terminals, and first to third supply terminals applied with first to third supply voltages, respectively. The third supply voltage is set a voltage between the first and second supply voltages. The differential amplifier circuit differentially receives signals of the input and output terminals. The output amplifier circuit includes first and second transistors of different conduction type each other coupled in series between the first and third supply terminals via the output terminal, and having control terminals coupled to first and second output nodes of the differential amplifier circuit, respectively. The control circuit includes a third transistor and a switch, and controls the third transistor being in a diode coupling mode between the first supply terminal and the control terminal of the first transistor for a given period of the output period.

摘要翻译： 输出电路分别包括差分放大器电路，输出放大器电路，控制电路，输入和输出端子以及分别施加有第一至第三电源电压的第一至第三电源端子。 第三电源电压设置在第一和第二电源电压之间的电压。 差分放大器电路差分地接收输入和输出端子的信号。 输出放大器电路包括不同导电类型的第一和第二晶体管，其彼此经由输出端串联耦合在第一和第三电源端子之间，并且具有分别耦合到差分放大器电路的第一和第二输出节点的控制端子。 控制电路包括第三晶体管和开关，并且在输出周期的给定时段内，控制第一晶体管的第一晶体管与第一晶体管的控制端之间的二极管耦合模式中的第三晶体管。

公开(公告)号：US20110234571A1

公开(公告)日：2011-09-29

申请号：US13064354

申请日：2011-03-21

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2330/028

摘要： Reference voltages of a reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is a power of 2 inclusive of 1 and z is a power of 2 plus 1. A decoder includes first to (z×S+1)th sub-decoders provided in association with the first to (z×S+1)th reference voltage groups, and a (z×S+1) input and 2 output type sub-decoder. The first to (z×S+1)th sub-decoders select, from the reference voltage of the first to the (z×S+1)th reference voltage groups, those reference voltages allocated to columns in a two-dimensional array of the reference voltages associated with the values of a first bit group of an input digital signal. The (z×S+1) input and 2 output sub-decoder receives outputs of the first to (z×S+1)th sub-decoders to select the first and second voltages from the reference voltages selected by the first to (z×S+1)th sub-decoders in response to the value of a second bit group of the input digital signal. An interpolation circuit receives the first and second voltages, selected by the decoder, to output a voltage level obtained on interpolation with an interpolation ratio of 1:1 (FIG. 1).

摘要翻译： 参考电压集合的参考电压被分类为第一至第（z×S + 1）个参考电压组，其中S是2的功率，包括1，z是2加1的功率。解码器包括首先（ 和第（z×S + 1）个输入型子解码器相关联地设置的z×S + 1个子解码器。 第一至第（Z×S + 1）子解码器从第一至第（z×S + 1）个参考电压组的参考电压中选择分配给二维阵列中的列的参考电压 与输入数字信号的第一位组的值相关联的参考电压。 （z×S + 1）输入和2输出子解码器接收第一至第（Z×S + 1）个子解码器的输出，以从由第一至第（z） ×S + 1）个子解码器，响应于输入数字信号的第二位组的值。 接收由解码器选择的第一和第二电压的插值电路，以1：1（图1）的插值比率输出以内插获得的电压电平。

公开(公告)号：US20110080214A1

公开(公告)日：2011-04-07

申请号：US12899149

申请日：2010-10-06

申请人： Hiroshi TSUCHI

发明人： Hiroshi TSUCHI

IPC分类号： H03F3/45

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2320/0223 ,  G09G2330/021

摘要： An output amplifier includes a differential stage having a reference voltage supplied to a first input, a first output stage that receives an output of the differential stage, a second output stage whose output is connected to a load, a capacitor element having a first end connected to a second input of the differential stage, and connection control circuits that control switching of first and second connection modes. In the first connection mode, there are provided a non-conductive state between output of the differential stage and input of the second output stage, a non-conductive state between output of the first output stage and output of the second output stage, a conductive state between output of the first output stage and the second input of the differential stage, and voltage of a second end of the capacitor element is an input voltage from the input terminal. In the second connection mode, there are provided a conductive state between output of the differential stage and input of the second output stage, a conductive state between output of the first output stage and output of the second output stage; a non-conductive state between output of the first output stage and the second input of the differential stage, a non-conductive state of the second end of the capacitor element from the input terminal, and a conductive state between the output of the first output stage and the second end of the capacitor element.

摘要翻译： 输出放大器包括具有提供给第一输入的参考电压的差分级，接收差分级的输出的第一输出级，输出连接到负载的第二输出级，具有第一端连接的电容元件 到差分级的第二输入端，以及控制第一和第二连接模式的切换的连接控制电路。 在第一连接模式中，提供差分级的输出与第二输出级的输入之间的非导通状态，第一输出级的输出与第二输出级的输出之间的非导通状态，导电 状态在第一输出级的输出和差分级的第二输入之间，并且电容器元件的第二端的电压是来自输入端的输入电压。 在第二连接模式中，提供差动级的输出与第二输出级的输入之间的导通状态，第一输出级的输出与第二输出级的输出之间的导通状态; 在所述第一输出级的输出与所述差动级的所述第二输入之间的非导通状态，所述电容器元件从所述输入端子的第二端的非导通状态以及所述第一输出端的输出之间的导通状态 阶段和电容器元件的第二端。

公开(公告)号：US07847718B2

公开(公告)日：2010-12-07

申请号：US11633518

申请日：2006-12-05

申请人： Junichiro Ishii ,  Hiroshi Tsuchi

发明人： Junichiro Ishii ,  Hiroshi Tsuchi

IPC分类号： H03M1/66

CPC分类号： H03M1/0646 ,  G09G3/2011 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2320/0276 ,  H03M1/76

摘要： A digital-to-analog converter including includes a decoder which receives m (where m>=4 holds) reference voltages having voltage values that differ from one another, and selects and outputs n (where n>=3 holds) identical or different voltages from among the m reference voltages based upon a digital signal; and an amplifying circuit that outputs a voltage, which is obtained by taking the weighted mean of the selected n voltages at a ratio of 2n−1:2n−2: . . . :20, from an output terminal.

摘要翻译： 一种数模转换器包括一个接收m（其中m≥4）的解码器，其具有彼此不同的电压值的参考电压，并且选择并输出n（其中n≥3）保持相同或不同的电压 基于数字信号的m个参考电压; 以及放大电路，输出通过以2n-1：2n-2：的比例取所选择的n个电压的加权平均值而得到的电压。 。 。 ：20，从输出端子。

公开(公告)号：US20100271348A1

公开(公告)日：2010-10-28

申请号：US12662459

申请日：2010-04-19

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G3/30 ,  G09G5/00

CPC分类号： G09G3/3291 ,  G09G2310/027

摘要： There is provided a decoder in which a matrix of transistors, a plurality of reference voltage signal lines arranged on a first interconnect layer and extended in a row direction, being separated to one another over the matrix, and a plurality of reference voltage signal lines arranged on a second interconnect layer and extended in the row direction, being separated to one another over the matrix. The reference voltage signal lines on the mutually different layers are respectively connected to impurity diffusion layers of the transistors that are adjacent in the row direction. The reference voltage signal lines on the mutually different layers are respectively connected to the impurity diffusion layers of the transistors that are adjacent in a column direction

摘要翻译： 提供了一种解码器，其中晶体管矩阵，布置在第一互连层上并沿行方向延伸的多个参考电压信号线在矩阵上彼此分离，并且布置多个参考电压信号线 在第二互连层上并在行方向上延伸，在矩阵上彼此分离。 相互不同的层上的参考电压信号线分别连接到在行方向上相邻的晶体管的杂质扩散层。 相互不同层上的参考电压信号线分别连接到在列方向上相邻的晶体管的杂质扩散层

公开(公告)号：US07808416B2

公开(公告)日：2010-10-05

申请号：US11539898

申请日：2006-10-10

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03M1/66

CPC分类号： G09G3/3696 ,  G09G3/3688 ,  G09G2310/027 ,  H03M1/765

摘要： A selection circuit receives a plural number (m) of respective different values of voltages as reference voltages to select and output two voltages. An amplifier receives at two input terminals the two reference voltages output from the selection circuit to output an output voltage extrapolated.

摘要翻译： 选择电路接收多个（m）个不同的电压值作为参考电压，以选择和输出两个电压。 放大器在两个输入端接收从选择电路输出的两个参考电压，以输出推断的输出电压。

公开(公告)号：US07761120B2

公开(公告)日：2010-07-20

申请号：US11480457

申请日：2006-07-05

申请人： Hiroshi Tsuchi ,  Kohei Okamoto ,  Toshio Watanabe ,  Yoshikazu Seko ,  Seiichi Suzuki

发明人： Hiroshi Tsuchi ,  Kohei Okamoto ,  Toshio Watanabe ,  Yoshikazu Seko ,  Seiichi Suzuki

IPC分类号： H04B1/38

CPC分类号： G09G3/2011 ,  G09G3/3648 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2330/021 ,  G09G2330/022 ,  H04W52/027 ,  Y02D70/122 ,  Y02D70/26

摘要： In a mobile phone having a liquid crystal display unit, the entire liquid crystal display unit is displayed in a simple display mode at lest in a non-operating standby mode. In the simple display mode, the entire liquid crystal display unit is driven by reducing the number of gradation levels or by decreasing a liquid crystal driving voltage. By using such a controlling method, the power consumption of the liquid crystal display unit can be reduced in the non-operating standby mode. On the other hand, necessary information such as time and the amount of remaining battery is displayed such that the information can be read.

摘要翻译： 在具有液晶显示单元的移动电话中，整个液晶显示单元以简单的显示模式以非操作待机模式被显示。 在简单显示模式下，通过减少灰度级数或通过降低液晶驱动电压来驱动整个液晶显示单元。 通过使用这种控制方法，可以在非操作待机模式下降低液晶显示单元的功耗。 另一方面，显示诸如时间和剩余电量的必要信息，使得可以读取信息。

公开(公告)号：US20090273618A1

公开(公告)日：2009-11-05

申请号：US12458333

申请日：2009-07-08

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G5/10

CPC分类号： H03M1/682 ,  G09G3/3685 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2320/0673 ,  H03M1/765

摘要： A data driver having a positive-polarity reference voltage generation circuit, a positive-polarity decoder, a first amplifier that outputs a positive-polarity gray scale voltage, a negative-polarity reference voltage generation circuit that generates a plurality of negative-polarity reference voltages, a negative-polarity decoder that outputs first to nth negative-polarity reference voltages from among the negative-polarity reference voltages, a negative-polarity amplifier that receives the selected first to nth negative-polarity reference voltages and outputs a negative-polarity gray scale voltage, and an output switch circuit that switches and controls whether to directly connect the first output terminal and the second output terminal to first and second data lines, respectively, or to cross-connect the first output terminal and the second output terminal to the second data line and the first data line, respectively, based on a control signal.

摘要翻译： 具有正极参考电压产生电路，正极性解码器，输出正极性灰度电压的第一放大器的数据驱动器，产生多个负极性参考电压的负极性参考电压产生电路 ，负极性解码器，从负极性参考电压输出第一至第n负极参考电压;负极性放大器，其接收所选择的第一至第n负极参考电压，并输出负极性灰度级 电压和输出开关电路，其分别切换和控制是否将第一输出端子和第二输出端子直接连接到第一和第二数据线，或者将第一输出端子和第二输出端子交叉连接到第二输出端子 数据线和第一数据线，分别基于控制信号。