Abstract:
Direct memory access is provided for each member of a group of IO devices organized into groups. Direct memory access for each IO device is performed in a predetermined order based on the predetermined groups, and may be completed by notification by an interrupt request. A predetermined time delay may be specified between each memory access by each IO device of a predetermined group.
Abstract:
The present invention provides apparatus and methods to perform thermal management in a computing environment. Thermal attributes are associated with operations and/or processing components. The components have thermal thresholds that should not be exceeded. In a preferred embodiment, an operation can be transferred from one component to another component if the thermal threshold is exceeded during execution by the first component.
Abstract:
A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least important processor as far as task priority is concerned, it will then select and transfer its interrupt-related responsibilities (i.e., handling the interrupt and determining the next interrupt-handing processor) to the processor which is executing the least important task. The selected processor will then be designated for handling interrupts unless and until it undergoes a task switch and selects a different processor.
Abstract:
A debugger 100 is connected to a multi-processor system configured so that each processor autonomously accesses a shared memory and loads a program stored in the shared memory into storage of the processor. An identifier defined uniquely in the system is included in code of the program module in advance. A GUID detector 118 selects an ID-attached instruction, the identifier being described in a field of the instruction, from the memory image of the local memory of the processor to be inspected and extracts the identifier. A code retriever 120 selects code of a program module, corresponding to the extracted identifier, from a code holder 114. A memory layout output unit 122 outputs the code selected by the code retriever 120, while associating the code with a memory address of the module in the local memory.
Abstract:
A system and method is provided for improved interrupt handling via a micro interrupt handler. Upon an interrupt signal being sent to a processor running a task, a first part of the running task is stored to system memory via direct memory access. A micro interrupt handler is read from the system memory to begin handling the interrupt signal. A second part of the running task is stored to system memory via direct memory access. The micro interrupt handler is executed and read and the previous running task is read from direct memory access and restored. Long lag times for interrupt processing and inefficiencies in processor queues are avoided.
Abstract:
Provides a diagnostic apparatus for diagnosing a measured object based on time-series data of a plurality of parameters measured from the measured object. An example of an apparatus includes a change-point score calculating portion for calculating a time-series change-point score with which each of the plurality of parameters changes according to passage of time based on the time-series data on the parameter, a change-point correlation calculating portion for calculating a change-point correlation indicating strength by which each of the plurality of parameters is associated with each of other parameters based on the change-point scores of the parameter and the other parameter, and a parameter outputting portion for outputting a set of parameters of which calculated degrees of associations are higher than a predetermined reference change-point correlation as a set of mutually strongly associated parameters.
Abstract:
Methods and apparatus are provided for managing processor tasks in a multi-processor computing system. The system is operable to store the processor tasks in a shared memory that may be accessed by a plurality of sub-processing units of the multi-processor computing system; and permit the sub-processing units to determine which of the processor tasks should be copied from the shared memory and executed based on priorities of the processor tasks.
Abstract:
Methods and apparatus are provided for executing processor tasks on a multi-processing system. The multi-processing system includes a plurality of sub-processing units and a main processing unit that may access a shared memory. Each sub-processing unit includes an on-chip local memory separate from the shared memory. The methods and apparatus contemplate: providing that the processor tasks be copied from the shared memory into the local memory of the sub-processing units in order to execute them, and prohibiting the execution of the processor tasks from the shared memory; and migrating at least one processor task from one of the sub-processing units to another of the sub-processing units.
Abstract:
[Object] To provide a shape generation apparatus, a control method to cause a computer apparatus to operate as a shape generation apparatus and computer executable programs to allow a computer apparatus to execute the control method. [Solution] The shape generation apparatus of this invention has an input model storage part 20 to store 3-dimensional input model data, an adjacency graph storage part 22 to store adjacency graph data generated by assigning face clusters to the input model, and a cluster coupling part 28 which executes coupling processing for the face clusters of the adjacency graph data. In addition, the shape generation apparatus also has a topology judgment part 30, which reads out the adjacency graph data and judges topology of the adjacency graph data read out, and a topology operation part 34, which changes node or arc data of the adjacency graph data in response to the judgment of the topology judgment part.