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    Semiconductor memory having electrically erasable and programmable semiconductor memory cells
    91.
    发明授权
    Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
    具有电可擦除和可编程的半导体存储器单元的半导体存储器

    公开(公告)号：US08331153B2

    公开(公告)日：2012-12-11

    申请号：US13363400

    申请日：2012-02-01

    Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

    Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

    IPC: G11C16/04

    CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

    Abstract: In a nonvolatile memory apparatus, a system bus receives address, command, and/or control signals. Memory cells store bits of data by shifting a threshold voltage to one of plural ranges. In writing a first page, the threshold voltage of a first memory cell remains in a first range or shifts into a second range. In writing a second page, the threshold voltage remains in the first or second voltages, or shifts into a third range from the first range or into a fourth range from the second range. Before writing the second page, the memory reads data from the first memory cell for generating the second page writing data. A shifting direction of the threshold voltage from the first to the second range is the same as a shifting direction from the first to the third range.

    Abstract translation: 在非易失性存储装置中，系统总线接收地址，命令和/或控制信号。 存储单元通过将阈值电压移位到多个范围之一来存储数据位。 在写入第一页时，第一存储器单元的阈值电压保持在第一范围或者移位到第二范围。 在写第二页时，阈值电压保持在第一或第二电压中，或者从第二范围移动到从第一范围到第四范围的第三范围。 在写入第二页之前，存储器从第一存储器单元读取用于生成第二页写入数据的数据。 从第一到第二范围的阈值电压的移动方向与从第一到第三范围的移动方向相同。

    SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS
    92.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING FAULTY CELLS 有权
    具有故障细胞的半导体存储器件

    公开(公告)号：US20100177579A1

    公开(公告)日：2010-07-15

    申请号：US12615502

    申请日：2009-11-10

    Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

    Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

    IPC: G11C29/04

    CPC classification number: G11C16/349 ,  G11C29/76 ,  G11C29/88

    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

    Abstract translation: 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

    Semiconductor memory having electrically erasable and programmable semiconductor memory cells
    94.
    发明授权
    Semiconductor memory having electrically erasable and programmable semiconductor memory cells 失效
    具有电可擦除和可编程的半导体存储器单元的半导体存储器

    公开(公告)号：US07570515B2

    公开(公告)日：2009-08-04

    申请号：US11870196

    申请日：2007-10-10

    Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

    Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

    IPC: G11C16/04

    CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

    Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

    Abstract translation: 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

    Semiconductor memory having electrically erasable and programmable semiconductor memory cells
    95.
    发明授权
    Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
    具有电可擦除和可编程的半导体存储器单元的半导体存储器

    公开(公告)号：US07295467B2

    公开(公告)日：2007-11-13

    申请号：US11206995

    申请日：2005-08-19

    Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

    Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

    IPC: G11C16/04

    CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

    Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

    Abstract translation: 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

    Image recording system and relay apparatus
    96.
    发明申请
    Image recording system and relay apparatus 审中-公开
    图像记录系统和中继装置

    公开(公告)号：US20050219601A1

    公开(公告)日：2005-10-06

    申请号：US11002705

    申请日：2004-12-01

    Applicant: Akira Tamagaki ,  Akihiko Taniguchi ,  Junichi Kajiwara ,  Takao Horiuchi ,  Yoshiomi Hamano ,  Kiyoshi Inoue ,  Hiroki Kai ,  Koichi Sumida ,  Yohichi Shimazawa

    Inventor： Akira Tamagaki ,  Akihiko Taniguchi ,  Junichi Kajiwara ,  Takao Horiuchi ,  Yoshiomi Hamano ,  Kiyoshi Inoue ,  Hiroki Kai ,  Koichi Sumida ,  Yohichi Shimazawa

    IPC: G06F3/12 ,  B41J3/407 ,  G03G21/04 ,  G06F15/00 ,  G06K9/00 ,  G06T1/00 ,  H04N1/00 ,  H04N1/32 ,  H04N1/387 ,  H04N5/91

    CPC classification number: H04N1/32144 ,  H04N1/00278 ,  H04N2201/3205 ,  H04N2201/327 ,  H04N2201/3271

    Abstract: A relay apparatus (relay unit) is provided between a PC, from which image data is transmitted, and an image recording apparatus (image recording unit). The relay apparatus executes a process for correcting a color on the image data transmitted from the PC to the image recording apparatus. In addition, a storage unit of the relay apparatus stores unique information of the image recording apparatus, such as a production number. The relay apparatus executes processes for correcting the image data and for adding the unique information to the image data transmitted from the PC, and then transmits the processed image data to the image recording apparatus. Thus, realized is an image recording system and the relay apparatus, in which it is not necessary to provide a circuit which executes a process for embedding unique information in the image data in the image recording apparatus, so that deterioration in quality of the image caused by the unique information can be prevented as much as possible.

    Abstract translation: 在发送图像数据的PC与图像记录装置（图像记录单元）之间提供中继装置（中继单元）。 中继装置执行用于校正从PC发送到图像记录装置的图像数据的颜色的处理。 此外，中继装置的存储单元存储诸如生产号码的图像记录装置的唯一信息。 中继装置执行用于校正图像数据并将唯一信息添加到从PC发送的图像数据的处理，然后将处理的图像数据发送到图像记录装置。 因此，实现了一种图像记录系统和中继装置，其中不需要提供执行用于在图像记录装置中的图像数据中嵌入唯一信息的处理的电路，从而导致图像质量的劣化 可以通过独特的信息尽可能的防止。

    Nb3Ga multifilamentary superconducting wire and process for preparing the same
    98.
    发明授权
    Nb3Ga multifilamentary superconducting wire and process for preparing the same 失效
    Nb3Ga复丝超导线及其制备方法

    公开(公告)号：US06845254B2

    公开(公告)日：2005-01-18

    申请号：US10397198

    申请日：2003-03-27

    Applicant: Kiyoshi Inoue ,  Yasuo Iijima ,  Akihiro Kikuchi ,  Yuji Yoshida

    Inventor： Kiyoshi Inoue ,  Yasuo Iijima ,  Akihiro Kikuchi ,  Yuji Yoshida

    IPC: H01B13/00 ,  H01B12/10 ,  H01L39/14 ,  H01L39/24 ,  H01B12/00 ,  C21D1/00 ,  H01F6/00 ,  H01L39/00

    CPC classification number: H01L39/2409 ,  H01L39/14 ,  Y10T428/12438 ,  Y10T428/24132 ,  Y10T428/249927 ,  Y10T428/294

    Abstract: By rapidly heating a precursor wire having a multifilamentary structure in which multiple composite cores in which a composite compound of an Nb—Ga compound and Nb is embedded in Nb are embedded in Nb, Ta, Nb-base alloy or Ta-base alloy as a matrix material to a temperature range of 1400 to 2100° C. in 2 seconds, quenching the precursor wire at a rate of 5000° C./second or larger, and subjecting the precursor wire to additional heat treatment at a temperature range of 600 to 850° C. for 1 to 400 hours, a superconducting wire having a multifilamentary structure in which multiple composite cores in which a composite compound containing Nb3Ga of a stoichiometric composition embedded in Nb are embedded in Nb, Ta, Nb-base alloy or Ta-base alloy as a matrix material is obtained.

    Abstract translation: 通过快速加热具有多晶复合结构的前体丝，其中Nb，Ga化合物和Nb的复合化合物埋入Nb中的多个复合芯嵌入Nb，Ta，Nb基合金或Ta基合金中，作为 基体材料在2秒钟内达到1400〜2100℃的温度范围，以5000℃/秒以上的速度骤冷前体丝，并在600〜600℃的温度范围进行额外的热处理 在850℃下进行1〜400小时的超导线，其具有多根复合芯，其中含有Nb中含有化学计量组成的Nb 3 Ga的复合化合物的复合芯埋入Nb，Ta，Nb基合金或Ta- 得到基体合金作为基体材料。

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