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91.发明公开公开(公告)号：US20230384950A1
公开(公告)日：2023-11-30
申请号：US17825975
申请日：2022-05-26
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Frederic RUELLE , Michel JAOUEN
IPC: G06F3/06
CPC classification number: G06F3/062 , G06F3/064 , G06F3/0604 , G06F3/0679
Abstract: System, method, and circuitry for generating content for a programmable computing device based on user-selected memory regions. Contiguous regions that share memory access attributes are merged, interleaved contiguous regions that share at least one nested attribute are defined into combined regions, and remaining regions are defined as separate independent regions. A memory protection unit (MPU) region size closest to a size of each defined region is identified. If the start address of each region aligns with the address structure of the MPU region size, then those regions are assigned to MPU regions having the MPU region size; otherwise, another MPU size that aligns with the size of the regions is selected and those regions are assigned to MPU regions having that size. Content is generated to configure settings of MPU regions of the programmable computing device for the merged contiguous regions, the combined region, and the independent regions.
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公开(公告)号：US20230296651A1
公开(公告)日：2023-09-21
申请号：US18121695
申请日：2023-03-15
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Christophe BELET
CPC classification number: G01R19/0023 , H03F3/211 , G01R19/2509
Abstract: Load current consumption measured using a first resistor having a high resistive value and a second resistor having a low resistive value. Differential amplifiers, the outputs of which are coupled to analog-to-digital converters and to a processing circuit unit, are connected to each of the nodes of the resistors. Depending on the current level, the processing circuit unit advantageously selects one of the analog-to-digital converters to estimate the present consumption of current in the load. Each input terminal of a resistor is advantageously power supplied from a power amplifier and each power amplifier is advantageously driven by a control loop. For low load currents, the first amplifier associated with the first resistor power supplies the load through the resistors while, for high load currents, when this first amplifier saturates, the second amplifier associated with the second resistor, takes over from the first amplifier to continue to power supply the load.
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公开(公告)号：US11734415B2
公开(公告)日：2023-08-22
申请号：US16922120
申请日：2020-07-07
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Vincent Berthelot
CPC classification number: G06F21/53 , G06F12/1408 , G06F12/1466 , G06F21/602 , G06F21/606 , G06F21/72
Abstract: An embodiment integrated circuit comprises a first memory zone having a first level of access rights that is configured to store at least one first software application containing encrypted instructions, means for verifying the integrity of the first software application, an encryption/decryption means, for example a first logic circuit, that is configured to decrypt the encrypted instructions which are considered to exhibit integrity, a processing unit that is configured to execute the decrypted instructions, the first logic circuit being further configured to encrypt the data generated by the execution operation and a second means, for example a second logic circuit, that is configured to store the encrypted data in a second memory zone having a second level of access rights that is identical to the first level of access rights.
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公开(公告)号：US11636060B2
公开(公告)日：2023-04-25
申请号：US17075296
申请日：2020-10-20
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Amelie Delaunay
Abstract: An electronic device includes a connector (e.g., a USB connector), a first element configured to operate the connector as a host device connector, a second element configured to operate the connector as a peripheral device connector, and a third element configured to generate a first signal upon connection of the connector. The first signal is indicative of whether the device is to operate as a host device or a peripheral device.
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公开(公告)号：US20230006684A1
公开(公告)日：2023-01-05
申请号：US17807452
申请日：2022-06-17
Inventor： Laurent Meunier , Vincent Pascal Onde
Abstract: In an embodiment a method includes generating a low-frequency clock signal having a first frequency, in a standby mode and in a run mode of the CPU, generating a high-frequency clock signal having a second frequency higher than the first frequency, in the run mode, updating a value of the reference time base at each period of the low-frequency clock signal in the standby mode, and accessing the counter register with the high-frequency clock signal in the run mode.
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Patent Agency Ranking
公开(公告)号：US20220327193A1
公开(公告)日：2022-10-13
申请号：US17640680
申请日：2020-09-02
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Frederic Ruelle
Abstract: The present disclosure relates to a method for authenticating instructions and operands in an electronic system comprising a controller. The method includes extracting instructions and operands via a first circuit of the controller from at least a first memory internal to the controller using a matrix bus of the controller, collecting, on the matrix bus, via a second circuit internal to the controller, instructions and operands during their transmission to the first circuit, and generating a word representative of the instructions and operands.
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公开(公告)号：US20220206688A1
公开(公告)日：2022-06-30
申请号：US17558003
申请日：2021-12-21
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Frederic DARCEL
Abstract: A method includes receiving, by a device, of a control signal identifying a first application from among a plurality of compressed applications stored in a non-volatile memory of the device. The first application is stored in a first location of the non-volatile memory. The device decompresses the first application. The decompressing includes storing the decompressed first application into the non-volatile memory at least partially into the first location, and into a second location storing a second compressed application among the plurality of applications. The decompressed first application overwriting at least a portion of the second compressed application. The method may be performed as part of a customization process of an integrated circuit including the non-volatile memory.
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公开(公告)号：US20220147786A1
公开(公告)日：2022-05-12
申请号：US17520266
申请日：2021-11-05
Inventor： Frederic GOUABAU , Olivier ROUY
IPC: G06K19/073 , H05B45/10
Abstract: A connector that is configured to receive a smart card includes: a first contact configured to receive a power supply voltage and corresponding to a first (power supply) contact area of the smart card, a second contact configured to receive a reference voltage and corresponding to contact a second (reference voltage) contact area of the smart card, and a third contact corresponding to a three-state (input/output) contact area of the smart card. A first light-emitting diode having an anode coupled to the third contact and a cathode coupled to the second contact. A second light-emitting diode has a cathode coupled to the third contact and an anode coupled to the first contact. Turning on/off of the first and second light-emitting diode is controlled by the smart card through the signal at the three-state (input/output) contact area.
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公开(公告)号：US11264905B2
公开(公告)日：2022-03-01
申请号：US16983856
申请日：2020-08-03
Applicant: STMicroelectronics (Grand Ouest) SAS
Inventor： Lionel Cimaz
Abstract: An embodiment DC to DC conversion circuit comprises a DC to DC converter and a regulation circuit. The regulation circuit comprises a comparator configured to detect, during a discharge phase of the DC to DC converter, an overshoot period during which an output voltage of the DC to DC converter exceeds a target voltage, and a timer configured to measure a duration of the overshoot period.
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公开(公告)号：US20210160193A1
公开(公告)日：2021-05-27
申请号：US17100505
申请日：2020-11-20
Applicant: STMicroelectronics (Rousset) SAS , STMicroelectronics (Alps) SAS , STMicroelectronics (Grand Ouest) SAS
Inventor： Daniel Olson , Loic Pallardy , Nicolas Anquet
IPC: H04L12/933 , H04L12/24
Abstract: System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit coupled between the master pieces of equipment and the slave resources and capable of routing transactions between master pieces of equipment and slave resources. A first particular slave resource cooperates with an element of the system on a chip, for example a clock signal generator, and the element has the same access rights as those of the corresponding first particular slave resource.
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