公开(公告)号：US11386518B2

公开(公告)日：2022-07-12

申请号：US16580654

申请日：2019-09-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Michael Mantor ,  Alexander Fuad Ashkar ,  Randy Ramsey ,  Mangesh P. Nijasure ,  Brian Emberling

IPC: G06T15/00 ,  G06T1/20 ,  G06F9/38 ,  G06T15/80

Abstract: The address of the draw or dispatch packet responsible for creating an exception is tied to a shader/wavefront back to the draw command from which it originated. In various embodiments, a method of operating a graphics pipeline and exception handling includes receiving, at a command processor of a graphics processing unit (GPU), an exception signal indicating an occurrence of a pipeline exception at a shader stage of a graphics pipeline. The shader stage generates an exception signal in response to a pipeline exception and transmits the exception signal to the command processor. The command processor determines, based on the exception signal, an address of a command packet responsible for the occurrence of the pipeline exception.

公开(公告)号：US11169811B2

公开(公告)日：2021-11-09

申请号：US16426613

申请日：2019-05-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rex Eldon McCrary ,  Yi Luo ,  Harry J. Wise ,  Alexander Fuad Ashkar ,  Michael Mantor

IPC: G06F9/38 ,  G06T1/60 ,  G06T1/20 ,  G06F16/245

Abstract: A method of context bouncing includes receiving, at a command processor of a graphics processing unit (GPU), a conditional execute packet providing a hash identifier corresponding to an encapsulated state. The encapsulated state includes one or more context state packets following the conditional execute packet. A command packet following the encapsulated state is executed based at least in part on determining whether the hash identifier of the encapsulated state matches one of a plurality of hash identifiers of active context states currently stored at the GPU.

公开(公告)号：US10656951B2

公开(公告)日：2020-05-19

申请号：US15789318

申请日：2017-10-20

Applicant: Advanced Micro Devices, Inc. ,  Advanced Micro Devices (Shanghai) Co., Ltd.

Inventor： Jiasheng Chen ,  YunXiao Zou ,  Bin He ,  Angel E. Socarras ,  QingCheng Wang ,  Wei Yuan ,  Michael Mantor

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F15/76

Abstract: A processing element is implemented in a stage of a pipeline and configured to execute an instruction. A first array of multiplexers is to provide information associated with the instruction to the processing element in response to the instruction being in a first set of instructions. A second array of multiplexers is to provide information associated with the instruction to the first processing element in response to the instruction being in a second set of instructions. A control unit is to gate at least one of power or a clock signal provided to the first array of multiplexers in response to the instruction being in the second set.

公开(公告)号：US10453243B2

公开(公告)日：2019-10-22

申请号：US16238727

申请日：2019-01-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirudh R. Acharya ,  Swapnil Sakharshete ,  Michael Mantor ,  Mangesh P. Nijasure ,  Todd Martin ,  Vineet Goel

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/80 ,  G06F9/50 ,  G06F9/48

Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.

公开(公告)号：US20180321946A1

公开(公告)日：2018-11-08

申请号：US16040224

申请日：2018-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Robert Scott Hartog ,  Mark Leather ,  Michael Mantor ,  Rex McCrary ,  Sebastien Nussbaum ,  Philip J. Rogers ,  Ralph Clay Taylor ,  Thomas Woller

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/48

CPC classification number: G06F9/3851 ,  G06F9/3879 ,  G06F9/4881 ,  G06T1/20

Abstract: A method for use in a processor for arbitrating between multiple processes to select wavefronts for execution on a shader core is provided. The processor includes a compute pipeline configured to issue wavefronts to the shader core for execution, a hardware queue descriptor associated with the compute pipeline, and the shader core. The shader core is configured to execute work for the compute pipeline corresponding to a first memory queue descriptor executed using data for the first memory queue descriptor that is loaded into a first hardware queue descriptor. The processor is configured to detect a context switch condition, and, responsive to the context switch condition, perform a context switch operation including loading data for a second memory queue descriptor into the first hardware queue descriptor. The shader core is configured to execute work corresponding to the second memory queue descriptor that is loaded into the first hardware queue descriptor.

公开(公告)号：US20180211435A1

公开(公告)日：2018-07-26

申请号：US15417063

申请日：2017-01-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Mangesh P. Nijasure ,  Todd Martin ,  Michael Mantor

IPC: G06T15/00 ,  G06T17/20 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06F9/44 ,  G06T11/40

Abstract: Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space pipeline. In either approach, the triangles output by the world-space pipelines are distributed to the screen-space pipelines based on the portions of the render surface overlapped by the triangles. Triangles are rendered by screen-space pipelines associated with the render surface portions overlapped by those triangles.

公开(公告)号：US20180211434A1

公开(公告)日：2018-07-26

申请号：US15415813

申请日：2017-01-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Mangesh P. Nijasure ,  Michael Mantor ,  Jeffrey M. Smith

IPC: G06T15/00 ,  G06T15/80 ,  G06T15/20 ,  G06T15/30

CPC classification number: G06T15/005 ,  G06T15/10 ,  G06T15/20 ,  G06T15/30 ,  G06T15/80 ,  H04N13/275

Abstract: Techniques for generating a stereo image from a single set of input geometry in a three-dimensional rendering pipeline are disclosed. Vertices are processed through the end of the world-space pipeline. In the primitive assembler, at the end of the world-space pipeline, before perspective division, each clip-space vertex is duplicated. The primitive assembler generates this duplicated clip-space vertex using the y, z, and w coordinates of the original vertex and based on an x coordinate that is offset in the x-direction in clip-space as compared with the x coordinate of the original vertex. Both the original vertex clip-space vertex and the modified clip-space vertex are then sent through the rest of the pipeline for processing, including perspective division, viewport transform, rasterization, pixel shading, and other operations. The result is that a single set of input vertices is rendered into a stereo image.

公开(公告)号：US20180113709A1

公开(公告)日：2018-04-26

申请号：US15342809

申请日：2016-11-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Bin He ,  YunXiao Zou ,  Jiasheng Chen ,  Michael Mantor

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3887 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3893

Abstract: A method and apparatus for performing a multi-precision computation in a plurality of arithmetic logic units (ALUs) includes pairing a first Single Instruction/Multiple Data (SIMD) block channel device with a second SIMD block channel device to create a first block pair having one-level staggering between the first and second channel devices. A third SIMD block channel device is paired with a fourth SIMD block channel device to create a second block pair having one-level staggering between the third and fourth channel devices. A plurality of source inputs are received at the first block pair and the second block pair. The first block pair computes a first result, and the second block pair computes a second result.

公开(公告)号：US20160260246A1

公开(公告)日：2016-09-08

申请号：US14635280

申请日：2015-03-02

Applicant: Advanced Micro Devices, Inc.

Inventor： David Oldcorn ,  Chris Brennan ,  Michael Mantor ,  Layla A. Mah

IPC: G06T15/80

CPC classification number: G06T15/80 ,  G06T1/20

Abstract: A method, a non-transitory computer readable medium, and a processor for performing display shading for computer graphics are presented. Frame data is received by a display shader, the frame data including at least a portion of a rendered frame. Parameters for modifying the frame data are received by the display shader. The parameters are applied to the frame data by the display shader to create a modified frame. The modified frame is displayed on a display device.

Abstract translation: 提出了一种方法，非暂时性计算机可读介质和用于执行计算机图形的显示阴影的处理器。 帧数据由显示着色器接收，帧数据包括渲染帧的至少一部分。 用于修改帧数据的参数由显示着色器接收。 通过显示着色器将参数应用于帧数据以创建修改的帧。 修改后的画面显示在显示设备上。