公开(公告)号：US06433579B1

公开(公告)日：2002-08-13

申请号：US09863143

申请日：2001-05-22

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Yan Chong ,  Philip Pan ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopinath Rangan

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Yan Chong ,  Philip Pan ,  Khai Nguyen ,  Joseph Huang ,  Xiaobao Wang ,  In Whan Kim ,  Gopinath Rangan

IPC分类号： H03K19177

CPC分类号： H03K19/17744 ,  H03K19/018521 ,  H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

摘要： A programmable logic device is equipped for various differential signaling schemes by providing a differential output buffer on the device that can be configured according to the needs of the particular differential signaling schemes that may be used. The buffer includes a differential output driver, an adjustable current limiting circuit between the supply voltage and the differential output driver, and an adjustable current limiting circuit between the differential output driver and ground. By selectively adjusting the two current limiting circuits, the output impedance and current, as well as the common mode output voltage and the differential output voltage can be controlled.

摘要翻译： 通过在设备上提供可根据可能使用的特定差分信令方案的需要进行配置的差分输出缓冲器，为各种差分信令方案配备了可编程逻辑器件。 缓冲器包括差分输出驱动器，电源电压和差分输出驱动器之间的可调节限流电路，以及差分输出驱动器和地之间的可调电流限制电路。 通过选择性地调节两个限流电路，可以控制输出阻抗和电流，以及共模输出电压和差分输出电压。

公开(公告)号：US07309906B1

公开(公告)日：2007-12-18

申请号：US11097503

申请日：2005-04-01

申请人： Jeffrey Tyhach ,  Bonnie I Wang ,  Yan Chong ,  Chiakang Sung

发明人： Jeffrey Tyhach ,  Bonnie I Wang ,  Yan Chong ,  Chiakang Sung

IPC分类号： H01L29/00 ,  H01L21/8242

CPC分类号： H01L29/94 ,  H01L27/0203

摘要： Improved decoupling capacitor designs and layout schemes are provided that generate high effective capacitance and high area efficiency at higher frequencies than that of previously known decoupling capacitor designs. The improved decoupling capacitor designs utilize transistor gates with shorter channel lengths to reduce the total parasitic resistance of the channel, thereby providing higher effective capacitance at higher frequencies. To enable higher area efficiency of this decoupling capacitor design, excess contacts are replaced with polysilicon in a grid or waffle pattern.

摘要翻译： 提供了改进的去耦电容器设计和布局方案，其在比先前已知的去耦电容器设计更高的频率下产生高有效电容和高的面积效率。 改进的去耦电容器设计利用具有较短沟道长度的晶体管栅极来减小沟道的总寄生电阻，从而在较高频率下提供更高的有效电容。 为了实现该去耦电容器设计的更高的面积效率，多余的触点被以栅格或华夫饼形式的多晶硅替代。