Clock switch-over circuits and methods
    93.
    发明授权
    Clock switch-over circuits and methods 有权
    时钟切换电路和方法

    公开(公告)号:US07911240B1

    公开(公告)日:2011-03-22

    申请号:US11750293

    申请日:2007-05-17

    IPC分类号: G06F1/08

    CPC分类号: G06F1/10

    摘要: Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

    摘要翻译: 时钟切换电路和方法为时钟路由网络提供时钟信号。 根据一个实施例,多路复用器响应于从控制电路接收的开关选择信号在第一时钟信号和第二时钟信号之间进行选择。 存储电路响应于多路复用器的输出时钟信号而存储使能信号。 响应于来自存储电路的使能信号,逻辑电路将多路复用器的输出时钟信号传输到时钟路由网络。 至少一个信号从时钟切换电路发送到控制电路。

    SYSTEMS AND METHODS FOR REDUCING STATIC AND TOTAL POWER CONSUMPTION
    96.
    发明申请
    SYSTEMS AND METHODS FOR REDUCING STATIC AND TOTAL POWER CONSUMPTION 失效
    减少静态和总功耗的系统和方法

    公开(公告)号:US20090138696A1

    公开(公告)日:2009-05-28

    申请号:US12329051

    申请日:2008-12-05

    IPC分类号: G06F1/32 G06F1/24

    CPC分类号: G06F1/32

    摘要: A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.

    摘要翻译: 提供了一种用于降低可编程逻辑器件(PLD)中功耗的方法和系统。 在可编程逻辑器件的技术映射,路由和后续周期期间,优选地可以连续地考虑功率消耗作为电路设计中的一个因素来降低功耗。

    Flexible RAM Clock Enable
    98.
    发明申请
    Flexible RAM Clock Enable 有权
    灵活的RAM时钟使能

    公开(公告)号:US20080253220A1

    公开(公告)日:2008-10-16

    申请号:US12145440

    申请日:2008-06-24

    IPC分类号: G11C8/18

    摘要: A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.

    摘要翻译: 第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。 第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

    Automatic adjustment of optimization effort in configuring programmable devices
    99.
    发明授权
    Automatic adjustment of optimization effort in configuring programmable devices 有权
    自动调整配置可编程设备的优化工作

    公开(公告)号:US07415682B2

    公开(公告)日:2008-08-19

    申请号:US11097592

    申请日:2005-04-01

    IPC分类号: G06F17/50 H03K17/693

    CPC分类号: G06F17/5054

    摘要: User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of the relative difficulty of the design goals is determined from the categories associated with the user design. Parameters of an optimization phase can be modified in accordance with this ranking to focus optimization efforts on specific design goals. The parameters may be weights of a cost function used by the optimization phase to evaluate alternative configurations of the user design. The user design can be re-classified into an additional category if the results of the optimization phase do not satisfy design goals, and additional optimization phases are selected based on this re-classification to further optimize the user design.

    摘要翻译: 用户设计被分配到与用户设计相关联的每个设计目标的类别。 每个类别代表满足设计目标的难度。 优化阶段根据类别的不同组合进行调整,并根据分配给用户设计的类别进行选择。 根据与用户设计相关的类别确定设计目标相对难度的排名。 优化阶段的参数可以根据这个排名进行修改,将优化工作集中在具体的设计目标上。 参数可以是优化阶段用于评估用户设计的替代配置的成本函数的权重。 如果优化阶段的结果不满足设计目标,则可以将用户设计重新分类为另外的类别,并且基于该重新分类来选择额外的优化阶段以进一步优化用户设计。