公开(公告)号：US07397726B1

公开(公告)日：2008-07-08

申请号：US11399771

申请日：2006-04-07

申请人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

发明人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

IPC分类号： G11C8/00 ,  G11C7/10

CPC分类号： G11C7/1075 ,  G11C8/18 ,  H03K19/1737

摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. The first set of configuration logic is also configurable to provide a first port core clock signal for controlling the memory block core. The first port core clock signal can either be the same as the first port input clock signal, or can be controlled independently from the first port input clock signal. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. The second set of configuration logic is also configurable to provide a second port core clock signal for controlling the memory block core. The second port core clock signal can be controlled independently from the second port input clock signal.

摘要翻译： 第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。 第一组配置逻辑也可配置为提供用于控制存储块核心的第一端口核心时钟信号。 第一个端口核心时钟信号可以与第一个端口输入时钟信号相同，也可以独立于第一个端口输入时钟信号进行控制。 第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。 第二组配置逻辑也可配置为提供用于控制存储块核心的第二端口核心时钟信号。 可以独立于第二端口输入时钟信号来控制第二端口核心时钟信号。

公开(公告)号：US20080253220A1

公开(公告)日：2008-10-16

申请号：US12145440

申请日：2008-06-24

申请人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

发明人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

IPC分类号： G11C8/18

CPC分类号： G11C7/1075 ,  G11C8/18 ,  H03K19/1737

摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.

摘要翻译： 第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。 第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

公开(公告)号：US08271821B2

公开(公告)日：2012-09-18

申请号：US12145440

申请日：2008-06-24

申请人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

发明人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

IPC分类号： G06F1/04 ,  G06F1/12

CPC分类号： G11C7/1075 ,  G11C8/18 ,  H03K19/1737

摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.

摘要翻译： 第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。 第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

公开(公告)号：US07725871B1

公开(公告)日：2010-05-25

申请号：US12123396

申请日：2008-05-19

申请人： Sean A. Safarpour ,  Gregg William Baeckler ,  Jinyong Yuan

发明人： Sean A. Safarpour ,  Gregg William Baeckler ,  Jinyong Yuan

IPC分类号： G06F17/50 ,  H03K19/00

CPC分类号： G06F17/5027

摘要： Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configuration passes this first phase, the approximation is refined to search for valid function implementations with the hardware configuration. The approximation and refinement may use a partitioning of function input variables to logic blocks to reduce the search space. Additional conflict clauses may be used to further reduce the search space. Implementations of sample functions or other previously considered functions may be analyzed to identify conflict clauses that are reusable for analyzing other functions. A representation of potential implementations of a function can be subdivided into subsets and analyzed separately. The intersection of the solutions from each subset are valid implementations of the function.

摘要翻译： 通过创建可编程逻辑块的硬件配置的近似来快速地筛选不太可能提供有效结果的配置来有效地确定具有可编程逻辑块的功能的有效实现。 如果配置通过此第一阶段，则会对该近似进行细化，以便通过硬件配置搜索有效的功能实现。 近似和细化可以使用功能输入变量对逻辑块的划分来减少搜索空间。 可以使用额外的冲突条款来进一步减少搜索空间。 可以分析样本函数或其他以前考虑的函数的实现，以识别可重用于分析其他函数的冲突条款。 功能的潜在实现的表示可以细分为子集并分开分析。 来自每个子集的解的交集是函数的有效实现。

公开(公告)号：US07249329B1

公开(公告)日：2007-07-24

申请号：US10859325

申请日：2004-06-01

申请人： Gregg William Baeckler ,  Jinyong Yuan ,  David W. Mendel

发明人： Gregg William Baeckler ,  Jinyong Yuan ,  David W. Mendel

IPC分类号： G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/505 ,  Y02T10/82

摘要： Technology mapping techniques for determining whether a function can be implemented using an incomplete lookup table (LUT) are provided. For example, the output of a function is compared to the output of an incomplete LUT for each binary value of the function's input signals and for each binary value of the bits stored in the incomplete LUT. For a LUT that is functionally asymmetric, the process can be repeated for multiple permutations of the input signals with respect to the input terminals of the LUT. As another example, the user function is converted into a network of multiplexers and complete LUTs, which are analyzed to determine if an incomplete LUT can implement the function. As another example, a truth table is constructed for a function. The truth table variables are then tested one by one as candidates for each input position using co-factoring and dependency checking.

摘要翻译： 提供了用于确定是否可以使用不完整查找表（LUT）来实现功能的技术映射技术。 例如，将函数的输出与功能输入信号的每个二进制值的不完整LUT的输出以及存储在不完全LUT中的位的每个二进制值进行比较。 对于功能不对称的LUT，相对于LUT的输入端，可以重复进行输入信号的多个排列的处理。 作为另一示例，用户功能被转换为多路复用器和完整LUT的网络，其被分析以确定不完整的LUT是否可以实现该功能。 作为另一示例，为功能构建真值表。 然后，将真值表变量逐个测试作为每个输入位置的候选，使用协同因子和依赖性检查。

公开(公告)号：US07246339B2

公开(公告)日：2007-07-17

申请号：US11101949

申请日：2005-04-08

申请人： Jinyong Yuan ,  Kar Keng Chua ,  Ji Park

发明人： Jinyong Yuan ,  Kar Keng Chua ,  Ji Park

IPC分类号： G06F17/50 ,  H03K17/693

CPC分类号： G06F17/5045

摘要： Structured ASICs that are equivalent to FPGA logic designs are produced by making use of a library of known structured ASIC equivalents to FPGA logic functions. Such a library is expanded by a process that searches new FPGA logic designs for logic functions that either do not already have structured ASIC equivalents in the library or for which possibly improved structured ASIC equivalents can now be devised. The new and/or improved structured ASIC equivalents are added to the library, preferably with version information in the case of FPGA logic functions for which more than one structured ASIC equivalent is known.

摘要翻译： 与FPGA逻辑设计相当的结构化ASIC通过利用FPGA逻辑功能的已知结构化ASIC等效的库来产生。 这样一个库可以通过一个过程来扩展，该过程可以搜索逻辑功能的新FPGA逻辑设计，这些逻辑功能在库中尚未具有结构化ASIC等价物，或者现在可以设计出可能改进的结构化ASIC等价物。 新的和/或改进的结构化ASIC等效物被添加到库中，优选地在FPGA逻辑功能的情况下具有已知多于一个结构化ASIC等效物的版本信息。

公开(公告)号：US07126858B1

公开(公告)日：2006-10-24

申请号：US11156083

申请日：2005-06-17

申请人： Jinyong Yuan ,  Peter Kazarian

发明人： Jinyong Yuan ,  Peter Kazarian

IPC分类号： G11C7/10

CPC分类号： G11C7/22

摘要： Circuitry is disclosed for emulating asynchronous clear on each of a read address register of a memory cell and a data output register of a memory cell such that the memory cell can be defined in a memory structure that does not support asynchronous clear capability. The emulation includes defining the memory cell to have a registered read address input and a data output connected to an input of a multiplexer. The register connected to the read address input of the multiplexer does not include an asynchronous clear connection. The data transmitted from the memory cell to the multiplexer is output from the multiplexer when an asynchronous clear signal has not been asserted. However, the multiplexer is further connected to output either null data or a ground signal in lieu of the data transmitted from the memory cell when an asynchronous clear signal has been asserted.

摘要翻译： 公开了用于在存储器单元的读地址寄存器和存储器单元的数据输出寄存器中的每一个上模拟异步清零的电路，使得可以在不支持异步清除能力的存储器结构中定义存储器单元。 仿真包括定义存储器单元以具有注册的读取地址输入和连接到多路复用器的输入的数据输出。 连接到多路复用器的读地址输入的寄存器不包括异步清除连接。 当异步清除信号尚未被断言时，从存储器单元发送到多路复用器的数据被从复用器输出。 然而，当异步清除信号被断言时，多路复用器进一步连接以输出空数据或接地信号来代替从存储器单元发送的数据。

公开(公告)号：US08397185B1

公开(公告)日：2013-03-12

申请号：US13461040

申请日：2012-05-01

申请人： Steven Perry ,  Jinyong Yuan ,  Shih-Yueh Lin ,  John R. Chase

发明人： Steven Perry ,  Jinyong Yuan ,  Shih-Yueh Lin ,  John R. Chase

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.

摘要翻译： 提供了可用于将源设备（例如可编程逻辑设计（PLD或FPGA））迁移到目标设备（诸如等效或替代专用集成电路（ASIC））中的图形用户辅助。 提供了一种设备选择器指南，用于在完成迁移之前评估从源设备到目标设备的迁移前景。

公开(公告)号：US08191020B1

公开(公告)日：2012-05-29

申请号：US12612479

申请日：2009-11-04

申请人： Steven Perry ,  Jinyong Yuan ,  Shih Yueh Lin ,  John R. Chase

发明人： Steven Perry ,  Jinyong Yuan ,  Shih Yueh Lin ,  John R. Chase

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A graphical user aid that may be used for migrating source devices, such as programmable logic designs (PLDs or FPGAs) into target devices, such as equivalent or substitute application-specific integrated circuits (“ASICs”) is provided. A device selector guide is provided for evaluating migration prospects from the source device to the target device before completing the migration.

摘要翻译： 提供了可用于将源设备（诸如可编程逻辑设计（PLD或FPGA））迁移到目标设备（诸如等效或代替应用专用集成电路（ASIC））中的图形用户辅助。 提供了一种设备选择器指南，用于在完成迁移之前评估从源设备到目标设备的迁移前景。

公开(公告)号：US07558812B1

公开(公告)日：2009-07-07

申请号：US10723104

申请日：2003-11-26

申请人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

发明人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

IPC分类号： G06F7/38

CPC分类号： G06F7/575 ,  H03K19/177 ,  H03K19/17728

摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

摘要翻译： 可编程逻辑器件（PLD）包括通过PLD路由架构连接的多个逻辑阵列块（LAB）。 至少一个LAB包括可配置为在多个级中算术组合多个二进制输入信号的逻辑元件（LE）。 LE包括具有K个输入（“K-LUT”）的查找表（LUT）逻辑。 K-LUT被配置为在K-LUT逻辑单元的相应输入处输入二进制输入信号，并且在K-LUT逻辑单元的多个输出处提供指示至少两个 二进制输入信号的算术组合的多级。 输入线网络包括输入线路网络，输入线路可配置为从PLD路由架构接收代表二进制输入信号的输入信号，并将输入信号提供给K-LUT。 输出线网络包括输出线网络，输出线路被配置为从K-LUT接收表示二进制结果信号的输出信号，并向PLD路由架构提供输出信号。 所描述的LUT可以有效地执行算术，以及非算术函数。