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183 条记录 (耗时 0.032 秒)

    Bit set modes for a resistive sense memory cell array
    91.
    发明授权
    Bit set modes for a resistive sense memory cell array 有权
    电阻读出存储单元阵列的位设置模式

    公开(公告)号：US08040713B2

    公开(公告)日：2011-10-18

    申请号：US12352693

    申请日：2009-01-13

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069

    摘要： Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

    摘要翻译： 本发明的各种实施例一般涉及一种用于为电阻式感测存储器（RSM）阵列提供不同的比特设置模式的方法和装置，诸如自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM） ）数组。 根据一些实施例，识别非易失性半导体存储器阵列中的一组RSM单元用于位设置操作的应用。 从对RSM单元分别写入的多个位设置值中选择位设置值，以将所述单元置于选择的电阻状态。 所选位设定值此后被写入所识别的组中的RSM单元的至少一部分。

    MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS
    92.
    发明申请
    MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS 有权
    存储器阵列，带有读参考电压电池

    公开(公告)号：US20110194330A1

    公开(公告)日：2011-08-11

    申请号：US13088610

    申请日：2011-04-18

    申请人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

    发明人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

    IPC分类号： G11C11/00

    CPC分类号： G11C7/14 ,  G11C11/1673

    摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

    摘要翻译： 本公开涉及具有读取参考电压单元的存储器阵列。 特别地，本公开涉及包括高电阻状态参考存储单元和低电阻状态参考存储单元的可变电阻存储单元设备和阵列，其提供片上可靠的平均参考电压以与所选择的存储器的读取电压进行比较 并确定所选存储单元是处于高电阻状态还是低电阻状态。 这些存储器阵列特别适用于自旋转移转矩存储单元，并且解决了与生成可靠参考电压有关的许多系统问题。

    Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array
    94.
    发明授权
    Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array 有权
    同时将多个可寻址的用户数据块写入电阻读出存储单元阵列

    公开(公告)号：US07944729B2

    公开(公告)日：2011-05-17

    申请号：US12360931

    申请日：2009-01-28

    申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Rod V. Bowman

    IPC分类号： G11C11/00

    CPC分类号： G11C8/06 ,  G06F11/1008 ,  G06F11/1076 ,  G11C8/04 ,  G11C11/1673 ,  G11C11/1675 ,  G11C29/44 ,  G11C29/76 ,  G11C2029/0411 ,  G11C2029/1208

    摘要： Method and apparatus are disclosed for storing data to non-volatile resistive sense memory (RSM) memory cells of a semiconductor memory array, including but not limited to resistive random access memory (RRAM) and spin-torque transfer random access memory (STTRAM or STRAM) cells. In accordance with various embodiments, a plurality of addressable data blocks from a host device are stored in a buffer. At least a portion of each of the addressable data blocks are serially transferred to a separate register of a plurality of registers. The transferred portions of said addressable data blocks are thereafter simultaneously transferred from the registers to selected RSM cells of the array.

    摘要翻译： 公开了用于将数据存储到半导体存储器阵列的非易失性电阻读出存储器（RSM）存储器单元的方法和装置，包括但不限于电阻随机存取存储器（RRAM）和自旋转矩传递随机存取存储器（STTRAM或STRAM ） 细胞。 根据各种实施例，来自主机设备的多个可寻址数据块被存储在缓冲器中。 每个可寻址数据块的至少一部分被串行地传送到多个寄存器的单独寄存器。 然后，所述可寻址数据块的传送部分从寄存器同时传送到阵列的所选RSM单元。

    Spatial Correlation of Reference Cells in Resistive Memory Array
    95.
    发明申请
    Spatial Correlation of Reference Cells in Resistive Memory Array 有权
    参考细胞在电阻记忆阵列中的空间相关性

    公开(公告)号：US20110080769A1

    公开(公告)日：2011-04-07

    申请号：US12968438

    申请日：2010-12-15

    申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

    发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

    IPC分类号： G11C11/00

    CPC分类号： G11C5/025 ,  G11C11/1653 ,  G11C11/1673

    摘要： The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.

    摘要翻译： 本公开涉及将参考列或参考行选择性地放置在存储器阵列中的方法。 该方法包括测量存储器阵列内的多个可变电阻存储器单元的电阻状态电阻值，并映射每个测量的可变电阻存储单元的位置，以形成多个可变电阻存储单元的电阻状态电阻值的映射 在内存阵列内。 然后，基于存储器阵列内的多个可变电阻存储器单元的电阻状态电阻值的映射来选择列或行作为参考列或参考行，以最小化读取操作错误，以及形成可变电阻存储器 单元存储器阵列。

    MRAM DIODE ARRAY AND ACCESS METHOD
    97.
    发明申请
    MRAM DIODE ARRAY AND ACCESS METHOD 有权
    MRAM二极管阵列和访问方法

    公开(公告)号：US20110058409A1

    公开(公告)日：2011-03-10

    申请号：US12948824

    申请日：2010-11-18

    申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Song S. Xue

    IPC分类号： G11C11/16 ,  G11C11/02

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： A memory unit includes a magnetic tunnel junction data cell is electrically coupled to a bit line and a source line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell. A first diode is electrically between the magnetic tunnel junction data cell and the source line and a second diode is electrically between the magnetic tunnel junction data cell and the source line. The first diode and second diode are in parallel electrical connection, and having opposing forward bias directions. The memory unit is configured to be precharged to a specified precharge voltage level and the precharge voltage is less than a threshold voltage of the first diode and second diode.

    摘要翻译： 存储单元包括磁性隧道结数据单元电耦合到位线和源极线。 磁隧道结数据单元被配置为通过使写入电流通过磁性隧道结数据单元而在高电阻状态和低电阻状态之间切换。 第一二极管电磁性地在磁性隧道结数据单元和源极线之间，第二个二极管电气地在磁性隧道结数据单元和源极线之间。 第一二极管和第二二极管并联电连接并具有相反的正向偏压方向。 存储器单元被配置为预充电到指定的预充电电压电平，并且预充电电压小于第一二极管和第二二极管的阈值电压。

    STATIS SOURCE PLANE IN STRAM
    98.
    发明申请
    STATIS SOURCE PLANE IN STRAM 有权
    统计资料来源：

    公开(公告)号：US20100302839A1

    公开(公告)日：2010-12-02

    申请号：US12855896

    申请日：2010-08-13

    申请人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Xuguang Wang

    发明人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Xuguang Wang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1675 ,  G11C11/1659

    摘要： A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.

    摘要翻译： 存储器阵列包括以2×2阵列排列的多个磁性隧道结单元。 每个磁性隧道结单元电耦合在位线和源极线之间，并且每个磁性隧道结单元电耦合到晶体管。 每个磁性隧道结单元被配置为通过使经过磁性隧道结单元的写入电流通过高电阻状态和低电阻状态之间切换。 第一字线电耦合到第一组晶体管的第一组的栅极，并且第二字线电耦合到第二组二个晶体管的栅极。 源极线是用于多个磁性隧道结的公共源极线。

    MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS
    99.
    发明申请
    MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS 有权

    公开(公告)号：US20100232211A1

    公开(公告)日：2010-09-16

    申请号：US12789691

    申请日：2010-05-28

    申请人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

    发明人： Hongyue Liu ,  Yong Lu ,  Andrew Carter ,  Yiran Chen ,  Hai Li

    IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C7/00

    CPC分类号： G11C7/14 ,  G11C11/1673

    摘要： The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.