公开(公告)号：US09299302B2

公开(公告)日：2016-03-29

申请号：US13581357

申请日：2011-04-07

申请人： Hajime Washio

发明人： Hajime Washio

IPC分类号： G09G3/36 ,  G09G3/20 ,  G02F1/1333

CPC分类号： G09G3/3648 ,  G02F2001/133388 ,  G09G3/2085 ,  G09G2300/0857

摘要： A normal display portion, in which image display is performed by typical active-matrix drive, and a memory display portion, in which image display is performed by memory drive are provided on a substrate which defines a liquid crystal panel. Each pixel in the memory display portion is shaped so as to include a curve or a side not parallel to either gate bus lines or source bus lines. A plurality of pixel memory units, each including a flip-flop, are provided so as to correspond to their respective pixels in the memory display portion. Display data is provided to the pixel memory unit that corresponds to the first stage of a shift register which is constituted by connecting the flip-flops in the plurality of pixel memory units in series.

摘要翻译： 在限定液晶面板的基板上设置有通过典型的有源矩阵驱动进行图像显示的正常显示部分和通过存储器驱动执行图像显示的存储器显示部分。 存储器显示部分中的每个像素被成形为包括不与任何一条栅极总线或源极总线线路平行的曲线或一侧。 提供了各自包括触发器的多个像素存储单元，以便与存储器显示部分中的它们各自的像素对应。 显示数据被提供给与通过串联连接多个像素存储器单元中的触发器而构成的移位寄存器的第一级对应的像素存储单元。

公开(公告)号：US09268175B2

公开(公告)日：2016-02-23

申请号：US14007618

申请日：2012-03-21

申请人： Katsutoshi Kikuchi ,  Masayuki Ohhashi ,  Hajime Washio

发明人： Katsutoshi Kikuchi ,  Masayuki Ohhashi ,  Hajime Washio

IPC分类号： G02F1/1339 ,  G02F1/1335 ,  G02B27/22 ,  H04N13/04 ,  G02F1/1333

CPC分类号： G02F1/1339 ,  G02B27/2214 ,  G02F1/133308 ,  G02F2201/503 ,  H04N13/31

摘要： A liquid crystal display device includes a display panel, a parallax barrier, and a spacer. The display panel includes a display area in which an image is displayed and a display surrounding area located around the display area. The parallax barrier includes a separation area and a separation surrounding area located around the separation area. The image displayed on the display panel is separated by parallax in the separation area. The parallax barrier is attached to the display panel with a space between the separation surrounding area of the parallax barrier and the display surrounding area of the display panel. The spacer is arranged in the space. The spacer is configured to define a distance between the display surrounding area of the display panel and the separation surrounding area of the parallax barrier.

摘要翻译： 液晶显示装置包括显示面板，视差屏障和间隔物。 显示面板包括其中显示图像的显示区域和位于显示区域周围的显示器周围区域。 视差屏障包括分离区域和位于分离区域周围的分离周围区域。 显示面板上显示的图像在分离区域中被视差分离。 视差屏障以视差屏障的分离周围区域和显示面板的显示器周围区域之间的间隔附着到显示面板。 间隔件布置在空间中。 间隔件被配置为限定显示面板的显示器周围区域与视差屏障的分离周围区域之间的距离。

公开(公告)号：US07791581B2

公开(公告)日：2010-09-07

申请号：US10714935

申请日：2003-11-18

申请人： Kazuhiro Maeda ,  Hajime Washio ,  Eiji Matsuda ,  Yuhichiroh Murakami

发明人： Kazuhiro Maeda ,  Hajime Washio ,  Eiji Matsuda ,  Yuhichiroh Murakami

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3607 ,  G09G3/3648 ,  G09G2300/0842 ,  G09G2310/027

摘要： In a shift register block according to the present invention, a plurality of flip-flops F/F(1), F/F(2), . . . F/F(n) constitute a shift register SR, and each adjacent ones of these flip-flops are therebetween having a corresponding one of waveform processing circuits WR(1) through WR(n), so that the shift register SR and the waveform processing circuits WR(1) and WR(n) are linearly aligned. With such an arrangment, it is possible to reduce area occupied by a signal line driving circuit including the shift register block, thereby narrowing the frame area of a display device.

摘要翻译： 在根据本发明的移位寄存器块中，多个触发器F / F（1），F / F（2）， 。 。 F / F（n）构成移位寄存器SR，并且这些触发器中的每个相邻的触发器之间具有对应的一个波形处理电路WR（1）至WR（n），使得移位寄存器SR和波形 处理电路WR（1）和WR（n）是直线对齐的。 通过这样的布置，可以减少包括移位寄存器块的信号线驱动电路所占用的面积，从而使显示装置的帧区域变窄。

公开(公告)号：US07741985B2

公开(公告)日：2010-06-22

申请号：US11793522

申请日：2006-01-11

申请人： Yasushi Kubota ,  Kazuhiro Maeda ,  Hajime Washio ,  Patrick Zebedee

发明人： Yasushi Kubota ,  Kazuhiro Maeda ,  Hajime Washio ,  Patrick Zebedee

IPC分类号： H03M1/66

CPC分类号： H03M1/802

摘要： A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n−1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.

摘要翻译： 一种数字/模拟转换器，用于转换其中n是大于1的整数的输入n位数字码，具有n位数字输入和用于连接到负载的输出，并且包括：（n-1） ）开关电容器; 和切换装置。 在一个示例性实施例中，切换装置在操作的归零阶段适于将第一参考电压连接到阵列的至少一个电容器的第一板，并将至少一个电容器的第二板连接到 电压，对于输入数字代码的至少一个值，与第一参考电压不同，并且在操作的解码阶段中进一步适应于使得能够依赖于输入数字代码的值将电荷注入 所述至少一个电容器。 在一个示例性实施例中，转换器可以是具有用于直接连接到电容性负载的输出的无缓冲转换器。

公开(公告)号：US20100103153A1

公开(公告)日：2010-04-29

申请号：US12654397

申请日：2009-12-18

申请人： Masakazu Satoh ,  Hajime Washio ,  Sadahiko Yasukawa

发明人： Masakazu Satoh ,  Hajime Washio ,  Sadahiko Yasukawa

IPC分类号： G09G5/00 ,  H04N3/00

CPC分类号： G09G3/3677 ,  G02F1/1362 ,  G09G2300/0452 ,  G09G2310/0218 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0209

摘要： A plurality of scanning signal lines GLn divided into groups, and each group is made up of three scanning signal lines GLnR, GLnG and GLnB, and a plurality of pixels are divided into pixel blocks, and each pixel block is made up of three pixels PR (n, m), PG (n, m) and PB (n, m) respectively connected to the scanning signal lines GLnR, GLnG and GLnB. These pixels PR (n, m), PG (n, m) and PB (n, m) are connected to a common data signal line SLm. To the scanning signal lines GLnR, GLnG, GLnB, scanning pulses are sequentially outputted to the scanning signal lines GLnR, GLnG and GLnB from shift registers SRnR, SRnG and SRnB, and video signals for R, G and B are outputted to the data signal line SLm from a driver IC by time division.

公开(公告)号：US07663613B2

公开(公告)日：2010-02-16

申请号：US10159288

申请日：2002-06-03

申请人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

发明人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： G09G5/00 ,  G06F3/038

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297

摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

摘要翻译： 图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。 信号线驱动电路中的存储电路和D / A转换电路通常用于n（“n”是等于或大于2的自然数）的信号线。 一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。 因此，可以驱动所有的信号线。 因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

公开(公告)号：US20090115771A1

公开(公告)日：2009-05-07

申请号：US12084766

申请日：2006-09-13

申请人： Hajime Washio

发明人： Hajime Washio

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3688

摘要： A data signal line drive circuit is provided with first sampling portions, and second sampling portions operated at a lower speed. By the action of selection circuits, the first sampling portions are operated during a normal display mode, and the second sampling portions are operated during a partial display mode. To ensure a correct sampling operation, one line time and a sampling interval are rendered longer during a display period of the partial display mode than during the normal display mode. During the normal display mode, both the first sampling portions and the second sampling portions may be operated. Thus, power consumption of a liquid crystal display device during the partial display is reduced.

摘要翻译： 数据信号线驱动电路设置有第一采样部分，第二采样部分以较低速度工作。 通过选择电路的动作，在正常显示模式下操作第一采样部分，并且在部分显示模式期间操作第二采样部分。 为了确保正确的采样操作，在部分显示模式的显示周期期间比在正常显示模式期间更长一段时间和采样间隔。 在正常显示模式期间，可以操作第一采样部分和第二采样部分。 因此，部分显示期间液晶显示装置的功耗降低。

公开(公告)号：US20090109203A1

公开(公告)日：2009-04-30

申请号：US12084763

申请日：2006-09-25

申请人： Hajime Washio ,  Michael James Brownlow

发明人： Hajime Washio ,  Michael James Brownlow

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3648 ,  G09G3/3688 ,  G09G2310/0294 ,  G09G2310/04 ,  G09G2330/021

摘要： A data signal line drive circuit is provided with first sampling portions, and second sampling portions operated at a lower speed. By the action of selection circuits, the first sampling portions are operated during a normal display mode, and the second sampling portions are operated during a partial display mode. To ensure a correct sampling operation, one line time and a sampling interval are rendered longer during a display period of the partial display mode than during the normal display mode. During the normal display mode, both the first sampling portions and the second sampling portions may be operated. Thus, power consumption of a liquid crystal display device during the partial display is reduced.

摘要翻译： 数据信号线驱动电路设置有第一采样部分，第二采样部分以较低速度工作。 通过选择电路的动作，在正常显示模式下操作第一采样部分，并且在部分显示模式期间操作第二采样部分。 为了确保正确的采样操作，在部分显示模式的显示周期期间比在正常显示模式期间更长一段时间和采样间隔。 在正常显示模式期间，可以操作第一采样部分和第二采样部分。 因此，部分显示期间液晶显示装置的功耗降低。

公开(公告)号：US07274351B2

公开(公告)日：2007-09-25

申请号：US10446149

申请日：2003-05-28

申请人： Hajime Washio ,  Shunsuke Hayashi

发明人： Hajime Washio ,  Shunsuke Hayashi

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0248

摘要： A driver circuit for a display device includes a plurality of set-reset flip-flops and switch circuits, and is arranged so that a timing pulse for sampling outputted from the flip-flop is supplied to the switch circuit, so as to cause the switch circuit to receive a clock signal. The clock signal operates as a set signal of the next stage flip-flop and outputted as a control signal for carrying out pre-charging of a data signal line and a selected pixel connected to the data signal line, with a switch. Thus, in case of performing pre-charging of a signal supplying line with an internal pre-charging circuit by using a pre-charging power source having small driving ability, this arrangement can provide a driver circuit for a display device capable of preventing fluctuation of a signal supplied to a different signal supplying line, while keeping the circuit scale of the shift register small.

摘要翻译： 用于显示装置的驱动器电路包括多个设定复位触发器和开关电路，并且被布置成使得从触发器输出的用于采样的定时脉冲被提供给开关电路，以便使开关 电路接收时钟信号。 时钟信号作为下一级触发器的设定信号工作，并作为控制信号输出，用于通过开关对数据信号线和连接到数据信号线的选择像素进行预充电。 因此，在通过使用具有小驱动能力的预充电电源来对信号供给线进行内部预充电电路的预充电的情况下，可以提供能够防止波动的显示装置的驱动电路 在保持移位寄存器的电路规模的同时，提供给不同信号供给线路的信号。

公开(公告)号：US07196699B1

公开(公告)日：2007-03-27

申请号：US09506033

申请日：2000-02-16

申请人： Yasushi Kubota ,  Hajime Washio ,  Ichiro Shiraki ,  Kazuhiro Maeda ,  Yasuyoshi Kaise

发明人： Yasushi Kubota ,  Hajime Washio ,  Ichiro Shiraki ,  Kazuhiro Maeda ,  Yasuyoshi Kaise

IPC分类号： G09G5/00 ,  G09G3/26 ,  H03K19/0175 ,  H03K19/00 ,  H03K5/153

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/021 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  G11C19/28

摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.

摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。 在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于 该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。 在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。 根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。