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    Digital to analogue converter
    1.
    发明授权
    Digital to analogue converter 失效
    数模转换器

    公开(公告)号：US07741985B2

    公开(公告)日：2010-06-22

    申请号：US11793522

    申请日：2006-01-11

    申请人： Yasushi Kubota ,  Kazuhiro Maeda ,  Hajime Washio ,  Patrick Zebedee

    发明人： Yasushi Kubota ,  Kazuhiro Maeda ,  Hajime Washio ,  Patrick Zebedee

    IPC分类号： H03M1/66

    CPC分类号： H03M1/802

    摘要： A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n−1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.

    摘要翻译： 一种数字/模拟转换器，用于转换其中n是大于1的整数的输入n位数字码，具有n位数字输入和用于连接到负载的输出，并且包括：（n-1） ）开关电容器; 和切换装置。 在一个示例性实施例中，切换装置在操作的归零阶段适于将第一参考电压连接到阵列的至少一个电容器的第一板，并将至少一个电容器的第二板连接到 电压，对于输入数字代码的至少一个值，与第一参考电压不同，并且在操作的解码阶段中进一步适应于使得能够依赖于输入数字代码的值将电荷注入 所述至少一个电容器。 在一个示例性实施例中，转换器可以是具有用于直接连接到电容性负载的输出的无缓冲转换器。

    DIGITAL TO ANALOGUE CONVERTER
    2.
    发明申请
    DIGITAL TO ANALOGUE CONVERTER 失效
    数字到模拟转换器

    公开(公告)号：US20090009374A1

    公开(公告)日：2009-01-08

    申请号：US11793522

    申请日：2006-01-11

    申请人： Yasushi Kubota ,  Kazuhiro Maeda ,  Hajime Washio ,  Patrick Zebedee

    发明人： Yasushi Kubota ,  Kazuhiro Maeda ,  Hajime Washio ,  Patrick Zebedee

    IPC分类号： H03M1/66

    CPC分类号： H03M1/802

    摘要： A digital/analogue converter for converting an input n-bit digital code, where n is an integer greater than one, has an n-bit digital input and an output for connection to a load, and includes: an array of (n−1) switched capacitors; and a switching arrangement. In one example embodiment, the switching arrangement is adapted, in a zeroing phase of operation, to connect a first reference voltage to the first plate of at least one capacitor of the array and to connect a second plate of the at least one capacitor to a voltage that, for at least one value of the input digital code, is different from the first reference voltage and is further adapted, in a decoding phase of operation, to enable, dependent on the value of the input digital code, injection of charge into the at least one capacitor. In one example embodiment, the converter may be a bufferless converter having an output for direct connection to a capacitive load.

    摘要翻译： 一种数字/模拟转换器，用于转换其中n是大于1的整数的输入n位数字码，具有n位数字输入和用于连接到负载的输出，并且包括：（n-1） ）开关电容器; 和切换装置。 在一个示例性实施例中，切换装置在操作的归零阶段适于将第一参考电压连接到阵列的至少一个电容器的第一板，并将至少一个电容器的第二板连接到 电压，对于输入数字代码的至少一个值，与第一参考电压不同，并且在操作的解码阶段中进一步适应于使得能够依赖于输入数字代码的值将电荷注入 所述至少一个电容器。 在一个示例性实施例中，转换器可以是具有用于直接连接到电容性负载的输出的无缓冲转换器。

    Shift register and image display apparatus using the same
    5.
    发明授权
    Shift register and image display apparatus using the same 有权
    移位寄存器和使用其的图像显示装置

    公开(公告)号：US06909417B2

    公开(公告)日：2005-06-21

    申请号：US09578440

    申请日：2000-05-25

    申请人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

    发明人： Hajime Washio ,  Yasushi Kubota ,  Kazuhiro Maeda ,  Yasuyoshi Kaise ,  Michael James Brownlow ,  Graham Andrew Cairns

    IPC分类号： G11C19/00 ,  G09G3/20 ,  G09G3/36

    CPC分类号： G09G3/3688 ,  G09G2300/0408 ,  G09G2310/0289 ,  G09G2330/021

    摘要： A level shifter 13 is provided for each of SR flip flops F1 constituting a shift register 11. The level shifter 13 increases a voltage of a clock signal CK. This arrangement reduces a distance for transmitting a clock signal whose voltage has been increased, as compared with a construction in which a voltage of a clock signal is increased by a single level shifter and the signal is transmitted to each of the flip flops; consequently, a load capacity of the level shifter can be smaller. Furthermore, each of the level shifters is operated during a pulse output of the previous level shifter 13, and the operation is suspended at the end of the pulse output. Thus, the level shifters 13 can operate only when it is necessary to apply a clock signal CK to the corresponding SR flip flop F1. As a result, even when an amplitude of a clock signal is small, it is possible to reduce power consumption of the shift resister under normal operation.

    摘要翻译： 为构成移位寄存器11的每个SR触发器F 1提供电平移位器13.电平移位器13增加时钟信号CK的电压。 与通过单个电平移位器增加时钟信号的电压并且将信号发送到每个触发器的结构相比，这种布置减少了用于传输电压已经增加的时钟信号的距离; 因此，电平转换器的负载能力可以更小。 此外，每个电平移位器在先前电平移位器13的脉冲输出期间操作，并且在脉冲输出结束时暂停操作。 因此，只有当需要对相应的SR触发器F 1施加时钟信号CK时，电平移位器13才能够工作。结果，即使当时钟信号的幅度小时，也可以降低功耗 的正常运行中的移位寄存器。

    Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices
    6.
    发明授权
    Shift register circuit, image display apparatus having the circuit, and driving method for LCD devices 有权
    移位寄存器电路，具有电路的图像显示装置以及LCD装置的驱动方法

    公开(公告)号：US06879313B1

    公开(公告)日：2005-04-12

    申请号：US09523511

    申请日：2000-03-10

    申请人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Kazuhiro Maeda ,  Hiroshi Yoneda

    发明人： Yasushi Kubota ,  Hajime Washio ,  Shigeto Yoshida ,  Kazuhiro Maeda ,  Hiroshi Yoneda

    IPC分类号： G09G3/36 ,  G11C19/28 ,  G11C19/00

    CPC分类号： G09G3/3688 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08 ,  G09G2320/0233 ,  G11C19/28

    摘要： A shift register circuit includes a plurality of latch circuits connected in series to sequentially transfer a pulse signal ST from one to another, a clock signal line transmitting a clock signal CLK, and a plurality of switching circuits performing electrical connection and disconnection between the clock signal line and the plurality of latch circuits. Upon turning on the shift register, at least one of the switching circuits electrically disconnects at least one of the latch circuits from the clock signal line. During an initialization period immediately after power has been turned on, the frequency of the clock signal CLK is lower than in a normal operation period and gradually increases toward the frequency used in the normal operation period.

    摘要翻译： 移位寄存器电路包括串联连接的多个锁存电路，以顺序地将脉冲信号ST从一个传送到另一个，一个发送时钟信号CLK的时钟信号线以及执行时钟信号之间的电连接和断开的多个开关电路 线和多个锁存电路。 在接通移位寄存器时，至少一个开关电路将至少一个锁存电路与时钟信号线电断开。 在电源接通之后的初始化期间，时钟信号CLK的频率比正常运行期间低，并且在正常运行期间逐渐增大。

    Digital-to-analog conversion circuit and image display apparatus using the same
    7.
    发明授权
    Digital-to-analog conversion circuit and image display apparatus using the same 有权
    数模转换电路和使用其的图像显示装置

    公开(公告)号：US06853324B2

    公开(公告)日：2005-02-08

    申请号：US09952183

    申请日：2001-09-13

    申请人： Kazuhiro Maeda ,  Yasushi Kubota ,  Hajime Washio

    发明人： Kazuhiro Maeda ,  Yasushi Kubota ,  Hajime Washio

    IPC分类号： G02F1/136 ,  G02F1/133 ,  G02F1/1368 ,  G09G3/20 ,  G09G3/36 ,  H03M1/74 ,  H03M1/80 ,  H03M1/66

    CPC分类号： H03M1/804 ,  G09G3/3688 ,  G09G2310/027

    摘要： A digital-to-analog conversion circuit of charge distribution type includes a plurality of capacitors having respective capacitances that increase in a sequential order, one end of the capacitors being commonly connected electrically. The circuit also includes a plurality of analog switches each for electrically connecting a reference potential corresponding to a digital signal inputted from outside to the other end of the corresponding capacitor. These analog switches have respective driving capacities that increase in a sequential order.

    摘要翻译： 电荷分配型的数模转换电路包括多个电容器，其具有各自依次增加的电容，电容器的一端电连接。 电路还包括多个模拟开关，每个模拟开关用于将与从外部输入的数字信号相对应的参考电位电连接到对应的电容器的另一端。 这些模拟开关具有按照顺序增加的各自的驱动能力。

    Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power
    8.
    发明授权
    Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权
    锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行

    公开(公告)号：US07196699B1

    公开(公告)日：2007-03-27

    申请号：US09506033

    申请日：2000-02-16

    申请人： Yasushi Kubota ,  Hajime Washio ,  Ichiro Shiraki ,  Kazuhiro Maeda ,  Yasuyoshi Kaise

    发明人： Yasushi Kubota ,  Hajime Washio ,  Ichiro Shiraki ,  Kazuhiro Maeda ,  Yasuyoshi Kaise

    IPC分类号： G09G5/00 ,  G09G3/26 ,  H03K19/0175 ,  H03K19/00 ,  H03K5/153

    CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2300/0408 ,  G09G2300/0417 ,  G09G2310/021 ,  G09G2310/0289 ,  G09G2330/021 ,  G11C19/00 ,  G11C19/28

    摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.

    摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。 在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于 该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。 在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。 根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。

    Image display device and display driving method
    9.
    发明授权
    Image display device and display driving method 失效

    公开(公告)号：US07079096B2

    公开(公告)日：2006-07-18

    申请号：US10253570

    申请日：2002-09-24

    申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Kazuhiro Maeda ,  Yasushi Kubota

    发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Kazuhiro Maeda ,  Yasushi Kubota

    IPC分类号： G09G3/36

    CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/0248

    摘要： Before a potential of counter electrode is changed, a potential holding circuit fixedly holds potentials of data signal lines S during a non-selective period of scanning signal lines G. This prevents the potentials of the data signal lines S from being an undesirably large potential, which is caused by coupling capacitors between the counter electrode and each data signal line S, whereby it is possible to supply to the pixel capacitor an electric charge corresponding to a gradation to be displayed, by using the relatively low potentials of the data signal lines S. This lowers a power supply voltage of a data signal driving circuit SD, thus reducing the electric power consumption. In short, with this arrangement, a liquid crystal display device can perform an opposed AC drive for line-inversion drive, frame-inversion drive and the like, by low power supply voltage of the data signal line driving circuit SD, thereby reducing the electric power consumption.

    Image display device and display driving method
    10.
    发明授权
    Image display device and display driving method 有权
    图像显示装置和显示驱动方法

    公开(公告)号：US06940500B2

    公开(公告)日：2005-09-06

    申请号：US10252497

    申请日：2002-09-23

    申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Kazuhiro Maeda ,  Yasushi Kubota

    发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Kazuhiro Maeda ,  Yasushi Kubota

    IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00

    CPC分类号： G09G3/3648 ,  G09G3/3688 ,  G09G2310/0248 ,  G09G2330/021

    摘要： A potential of a data signal line S during a scanning period is charged to a substantially intermediate potential of a data signal at a corresponding frame. Thus, extremely large dispersion does not occur in a potential of each pixel capacitor with respect to a potential of the data signal line S, so that it is possible to restrict dispersion of a leak current flowing via an active element of each pixel. Thus, potential variation of a pixel PIX is reduced, so that it is possible to improve display quality during a non-scanning period. That is, in an active-matrix-type liquid crystal display, when a frame frequency is reduced by setting the non-scanning period to be sufficiently larger than a scanning period while a standby image is being displayed so as to realize low power consumption, the display quality is improved.

    摘要翻译： 扫描周期期间的数据信号线S的电位被充电到相应帧的数据信号的大致中间电位。 因此，相对于数据信号线S的电位，每个像素电容器的电位不会发生极大的色散，从而可以限制流过每个像素的有源元件的漏电流的色散。 因此，像素PIX的电位变化减小，使得可以在非扫描期间提高显示质量。 也就是说，在有源矩阵型液晶显示器中，当通过在显示待机图像的同时将非扫描周期设置为比扫描周期充分大来降低帧频，从而实现低功耗， 显示质量得到提高。