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1.发明授权Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行公开(公告)号：US07196699B1
公开(公告)日：2007-03-27
申请号：US09506033
申请日：2000-02-16
IPC分类号： G09G5/00 , G09G3/26 , H03K19/0175 , H03K19/00 , H03K5/153
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。 在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于 该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。 在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。 根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。
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2.发明申请Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行公开(公告)号：US20050057556A1
公开(公告)日：2005-03-17
申请号：US10949990
申请日：2004-09-23
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。 在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于 该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。 在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。 根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。
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3.发明授权Latch circuit, shift register circuit and image display device operated with a low consumption of power 有权锁存电路，移位寄存器电路和图像显示设备以低功耗运行公开(公告)号：US06580411B1
公开(公告)日：2003-06-17
申请号：US09300178
申请日：1999-04-27
IPC分类号： G09G336
CPC分类号： H03K3/356121 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2310/0286 , G09G2320/0209 , G09G2320/0257 , G09G2330/021 , H03K3/356139
摘要： If a clock signal ck is “H” and an input pulse signal in (first control signal) is “H”, then n-type transistors M15 and M16 are turned on to make an output node/OUT have the GND level. Then, a p-type transistor M12 is turned on to make an output node OUT have a Vcc (16 V) level. Thus, a latch circuit LAT operates as a level shifter circuit when first and second control signals and the clock signal ck are at “H” and operates as a level hold circuit in any other case. Therefore, the shift register circuit constructed of the latch circuit LAT functions as a low-voltage interface, and the input of the clock signal ck is stopped when the latch circuit LAT is inactive, so that the load and the consumption of power of the clock signal line are reduced.
摘要翻译： 如果时钟信号ck为“H”，并且（第一控制信号）中的输入脉冲信号为“H”，则n型晶体管M15和M16导通，使输出节点/ OUT具有GND电平。 然后，p型晶体管M12导通，使得输出节点OUT具有Vcc（16V）电平。 因此，当第一和第二控制信号和时钟信号ck处于“H”时，锁存电路LAT作为电平移位器电路工作，并且在任何其它情况下作为电平保持电路工作。 因此，由锁存电路LAT构成的移位寄存器电路用作低电压接口，并且当锁存电路LAT不活动时，时钟信号ck的输入停止，使得时钟的负载和功率的消耗 信号线减少。
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4.发明授权Latch circuit, shift register circuit, logical circuit and image display device operated with a low consumption of power 有权锁存电路，移位寄存器电路，逻辑电路和图像显示设备以低功耗运行公开(公告)号：US07460099B2
公开(公告)日：2008-12-02
申请号：US10949990
申请日：2004-09-23
CPC分类号： G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0417 , G09G2310/021 , G09G2310/0289 , G09G2330/021 , G11C19/00 , G11C19/28
摘要： A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.
摘要翻译： CMOS逻辑电路包括两个电流路径，每个电路具有由n型和p型晶体管组成的电路。 在由n型或p型晶体管组成的电路中，一个电流路径设置有与具有CMOS逻辑电路的n型晶体管的电路相同结构的电路，该逻辑电路输出类似于 该逻辑电路的另一个电流路径具有与具有CMOS逻辑电路的p型晶体管的电路相同结构的电路，该电路输出类似于该逻辑电路的逻辑运算结果。 在由另一沟道型构成的另一电路中，设置在一个电流路径上的晶体管的栅电极和设置在另一电流路径上的晶体管的栅电极连接到对应物的漏电极。 根据该结构，可以使输入信号的幅度小于逻辑电路的电源电压。
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公开(公告)号：US6157361A
公开(公告)日：2000-12-05
申请号：US892157
申请日：1997-07-14
申请人： Yasushi Kubota , Ichiro Shiraki , Tamotsu Sakai
发明人： Yasushi Kubota , Ichiro Shiraki , Tamotsu Sakai
CPC分类号： G09G3/3674 , G09G3/3685 , G09G2300/0408 , G09G2310/0289 , G09G2310/06 , G09G3/20 , G09G3/3648 , H01L27/12 , H01L29/78
摘要： A matrix-type image display device of the present invention is arranged such that image data are selectively applied to pixels arranged in a matrix form through scanning signal lines and data signal lines, and the image data are stored therein, wherein a high potential of a sampling pulse 0V/5V to be output from a logic circuit is shifted to 10 V, and a low potential thereof is shifted to -8 V respectively by first and second level shifters. As a result, a difference between an input signal level from an external circuit such as a control circuit, an image signal processing circuit, etc., and an actual driving signal level of each pixel can be absorbed. Therefore, an additional structure such as an interface circuit, etc., is not needed between the external circuit and the scanning signal line driving circuit, thereby enabling a low cost and a low power consumption.
摘要翻译： 本发明的矩阵型图像显示装置被布置成使得图像数据被选择性地施加到通过扫描信号线和数据信号线以矩阵形式布置的像素，并且图像数据被存储在其中，其中高电位 从逻辑电路输出的采样脉冲0V / 5V被移位到10V，并且其低电位分别由第一和第二电平移位器移位到-8V。 结果，可以吸收来自诸如控制电路的外部电路的输入信号电平，图像信号处理电路等之间的差异和每个像素的实际驱动信号电平之间的差异。 因此，在外部电路和扫描信号线驱动电路之间不需要诸如接口电路等的附加结构，从而能够实现低成本和低功耗。
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公开(公告)号：US5926234A
公开(公告)日：1999-07-20
申请号：US877567
申请日：1997-06-17
申请人： Ichiro Shiraki , Yasushi Kubota , Hiroshi Yoneda
发明人： Ichiro Shiraki , Yasushi Kubota , Hiroshi Yoneda
IPC分类号： G02F1/136 , G02F1/133 , G02F1/1362 , G02F1/1368 , G09G3/36 , H01L29/78 , H01L29/786 , G02F1/1333 , G02F1/1345 , H01L23/62
CPC分类号： G02F1/13454 , G02F1/136204 , G02F2001/136254 , G09G3/3611 , H01L2924/0002
摘要： Picture elements and driving circuits for driving respective picture elements are monolithically formed on an insulating substrate. A protective circuit is provided for allowing input-output terminals of a driving circuit to conduct when a potential difference of not less than a predetermined value is generated. The protective circuit includes an MOS transistor, and a turn-on voltage thereof is set according to a thickness of a gate insulating layer. The protective circuit is formed on the insulating substrate simultaneously when forming the driving circuits. In this arrangement, because the turn-on voltage is set according to the thickness of the gate insulating layer and the thickness can be easily adjusted, an accurate turn-on voltage can be achieved. Since the arrangement prevents an increase in manufacturing cost, the driving circuits, etc., can be surely protected against static electricity generated in the manufacturing process and the input surge in the normal operation.
摘要翻译： 用于驱动各个像素的图像元件和驱动电路单片地形成在绝缘基板上。 提供保护电路，用于当产生不小于预定值的电位差时允许驱动电路的输入输出端子导通。 保护电路包括MOS晶体管，并且其导通电压根据栅绝缘层的厚度设定。 当形成驱动电路时，保护电路同时形成在绝缘基板上。 在这种布置中，由于根据栅极绝缘层的厚度设定导通电压并且可以容易地调节厚度，所以可以实现准确的导通电压。 由于该装置防止制造成本的增加，因此可以可靠地保护驱动电路等，以免在制造过程中产生的静电和正常操作中的输入浪涌。
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7.发明授权Semiconductor device, display device, and method for producing a semiconductor device 失效半导体装置，显示装置及半导体装置的制造方法公开(公告)号：US06465806B2
公开(公告)日：2002-10-15
申请号：US09095587
申请日：1998-06-11
申请人： Yasushi Kubota , Ichiro Shiraki , Tamotsu Sakai , Zhang Hongyong , Jun Koyama
发明人： Yasushi Kubota , Ichiro Shiraki , Tamotsu Sakai , Zhang Hongyong , Jun Koyama
IPC分类号： H01L2904
CPC分类号： H01L23/5226 , G02F1/1345 , G02F1/13454 , G09G3/3688 , H01L21/76838 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first conductive layer; an interlayer insulative layer having an opening; and a second conductive layer. The first conductive layer, the interlayer insulative layer and the second conductive layer are sequentially laminated. The opening is partially covered by the second conductive layer, and an area of the first conductive layer is substantially entirely covered by the second conductive layer in the opening.
摘要翻译： 半导体器件包括第一导电层; 具有开口的层间绝缘层; 和第二导电层。 第一导电层，层间绝缘层和第二导电层依次层叠。 开口部分被第二导电层覆盖，并且第一导电层的面积基本上完全被开口中的第二导电层覆盖。
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公开(公告)号：US06373460B1
公开(公告)日：2002-04-16
申请号：US09684912
申请日：2000-10-10
申请人： Yasushi Kubota , Ichiro Shiraki , Tamotsu Sakai
发明人： Yasushi Kubota , Ichiro Shiraki , Tamotsu Sakai
IPC分类号： G09G336
CPC分类号： G09G3/3674 , G09G3/20 , G09G3/3648 , G09G3/3685 , G09G2300/0408 , G09G2310/0289 , G09G2310/06 , H01L27/12 , H01L29/78
摘要： A matrix-type image display device of the present invention is arranged such that image data are selectively applied to pixels arranged in a matrix form through scanning signal lines and data signal lines, and the image data are stored therein, wherein a high potential of a sampling pulse 0V/5V to be output from a logic circuit is shifted to 10 V, and a low potential thereof is shifted to −8 V respectively by first and second level shifters. As a result, a difference between an input signal level from an external circuit such as a control circuit, an image signal processing circuit, etc., and an actual driving signal level of each pixel can be absorbed. Therefore, an additional structure such as an interface circuit, etc., is not needed between the external circuit and the scanning signal line driving circuit, thereby enabling a low cost and a low power consumption.
摘要翻译： 本发明的矩阵型图像显示装置被布置成使得图像数据被选择性地施加到通过扫描信号线和数据信号线以矩阵形式布置的像素，并且图像数据被存储在其中，其中高电位 从逻辑电路输出的采样脉冲0V / 5V被移位到10V，并且其低电位分别由第一和第二电平移位器移位到-8V。 结果，可以吸收来自诸如控制电路的外部电路的输入信号电平，图像信号处理电路等之间的差异和每个像素的实际驱动信号电平之间的差异。 因此，在外部电路和扫描信号线驱动电路之间不需要诸如接口电路等的附加结构，从而能够实现低成本和低功耗。
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公开(公告)号：US08305315B2
公开(公告)日：2012-11-06
申请号：US12733884
申请日：2008-06-19
IPC分类号： G09G3/36
CPC分类号： G09G3/20 , G02F1/13454 , G02F1/1368 , G02F2001/13606 , G09G3/3685 , G09G2310/0275 , G09G2310/0297 , G09G2330/021 , H01L27/124
摘要： The present invention aims to provide a monolithic driver-type display device capable of reducing circuit scale of a sampling circuit, and keeping low power consumption by directly driving a source driver with an externally provided video signal.In the monolithic driver-type display device having a display portion for displaying video and circuits for driving the display portion formed on the same insulating substrate, a plurality of sampling switches are provided in association with a plurality of pieces of bit data contained in externally inputted digital video signals. The sampling switches are opened/closed based on sampling signals, thereby sampling the digital video signals for each piece of the bit data and converting the signals into parallel format for output to data lines. The outputted digital video signals charge parasitic capacitances on the data lines and are held therein.
摘要翻译： 本发明的目的在于提供一种能够降低采样电路的电路规模的单片驱动型显示装置，并且通过用外部提供的视频信号直接驱动源极驱动器来保持低功耗。 在具有用于显示视频的显示部分和用于驱动形成在同一绝缘基板上的显示部分的电路的单片驱动型显示装置中，与外部输入的多个位数据相关联地提供多个采样开关 数字视频信号。 采样开关基于采样信号进行开/关，从而针对每一位数据采样数字视频信号，并将信号转换为并行格式以输出到数据线。 输出的数字视频信号对数据线上的寄生电容进行充电并保持在其中。
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公开(公告)号：US20110149174A1
公开(公告)日：2011-06-23
申请号：US13061545
申请日：2009-07-07
申请人： Kazuhiro Maeda , Ichiro Shiraki , Hiroaki Sugiyama
发明人： Kazuhiro Maeda , Ichiro Shiraki , Hiroaki Sugiyama
CPC分类号： G06F3/0412 , G02F2001/13312 , G09G3/3648 , G09G3/3688 , G09G2360/144 , G09G2360/148
摘要： A display device includes a photosensor (81) in a pixel region (1) of an active matrix substrate (100). The photosensor (81) includes a photodetection element, reset signal wiring that supplies a reset signal RS to the photosensor (81), readout signal wiring that supplies a readout signal RW to the photosensor (81), and a sensor switching element for reading out the potential of the storage node to output wiring as sensor circuit output, the potential of the storage node having changed in accordance with the amount of light received by the photodetection element in a sensing period, the sensing period being from when the reset signal is supplied until when the readout signal is supplied. The potential of wiring having a parasitic capacitance with the storage node is fixed to a predetermined potential V0 at least either one of immediately before the readout signal RW and immediately before the reset signal RS.
摘要翻译： 显示装置包括在有源矩阵基板（100）的像素区域（1）中的光电传感器（81）。 光传感器（81）包括光检测元件，向光传感器（81）提供复位信号RS的复位信号布线，向光电传感器（81）提供读出信号RW的读出信号布线和用于读出的传感器开关元件 存储节点输出布线作为传感器电路输出的电位，存储节点的电位根据在感测周期中由光电检测元件接收的光量而改变，感测周期是从复位信号提供时 直到提供读出信号为止。 具有与存储节点的寄生电容的布线的电位在紧接在读出信号RW之前和紧接在复位信号RS之前的至少一个中固定到预定电位V0。
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