公开(公告)号：US07663613B2

公开(公告)日：2010-02-16

申请号：US10159288

申请日：2002-06-03

申请人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

发明人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： G09G5/00 ,  G06F3/038

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297

摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

摘要翻译： 图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。 信号线驱动电路中的存储电路和D / A转换电路通常用于n（“n”是等于或大于2的自然数）的信号线。 一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。 因此，可以驱动所有的信号线。 因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

公开(公告)号：US08325170B2

公开(公告)日：2012-12-04

申请号：US12639049

申请日：2009-12-16

申请人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

发明人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： G09G5/00 ,  G06F3/038

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297

摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

摘要翻译： 图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。 信号线驱动电路中的存储电路和D / A转换电路通常用于n（n为等于或大于2的自然数）信号线。 一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。 因此，可以驱动所有的信号线。 因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

公开(公告)号：US20100090994A1

公开(公告)日：2010-04-15

申请号：US12639049

申请日：2009-12-16

申请人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

发明人： Yukio Tanaka ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： G09G5/00 ,  G09G3/36 ,  H04N5/66

CPC分类号： G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297

摘要： An occupying area of a digital system signal line driver circuit in an image display device is large and this hinders the miniaturization of the display device. A memory circuit and a D/A converter circuit in the signal line driver circuit are commonly used for n (“n” is a natural number equal to or larger than 2) signal lines. One horizontal scanning period is divided into n periods and the memory circuit and the D/A converter circuit each perform processing for different signal lines during each of the divided periods. Thus, all the signal lines can be driven. Therefore, the number of memory circuits and the number of D/A converter circuits in the signal line driver circuit can be reduced to one n-th in a conventional case.

摘要翻译： 图像显示装置中的数字系统信号线驱动电路的占有面积大，妨碍显示装置的小型化。 信号线驱动电路中的存储电路和D / A转换电路通常用于n（“n”是等于或大于2的自然数）的信号线。 一个水平扫描周期被分为n个周期，并且存储器电路和D / A转换器电路在每个分割周期期间各自执行不同信号线的处理。 因此，可以驱动所有的信号线。 因此，在常规情况下，信号线驱动电路中的存储电路数量和D / A转换电路的数量可以减少到1 / n。

公开(公告)号：US06693616B2

公开(公告)日：2004-02-17

申请号：US09782260

申请日：2001-02-14

申请人： Jun Koyama ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

发明人： Jun Koyama ,  Munehiro Azami ,  Yasushi Kubota ,  Hajime Washio

IPC分类号： G09G336

CPC分类号： G09G3/3688 ,  G09G2310/0259 ,  G09G2310/027 ,  G09G2310/0297

摘要： The surface area occupied by a digital type signal line driver circuit in an image display device is large, and this is an impediment to reducing the size of the display device. A memory circuit within a signal line driver circuit is made common among n signal lines (where n is a natural number greater than or equal to 2). One horizontal scan period is divided into n divisions, and all signal lines can be driven by performing processing with respect to signal lines differing by memory circuit and D/A converter circuit, respectively, during the period of each division. It thus becomes possible to make 1/n as many memory circuits and D/A conversion circuits within the signal line driver circuit as in a conventional example.

摘要翻译： 图像显示装置中的数字式信号线驱动电路所占据的表面积较大，这是减小显示装置尺寸的障碍。 信号线驱动电路内的存储电路在n条信号线（其中n为大于或等于2的自然数）之间是共同的。 一个水平扫描周期被划分为n个分区，并且在每个划分期间分别通过对与存储电路和D / A转换器电路不同的信号线执行处理来驱动所有的信号线。 因此，与现有例一样，能够使信号线驱动电路内的1 / n的存储电路和D / A转换电路成为可能。

公开(公告)号：US07550790B2

公开(公告)日：2009-06-23

申请号：US11709072

申请日：2007-02-22

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： H01L29/74

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

公开(公告)号：US06738005B2

公开(公告)日：2004-05-18

申请号：US10053656

申请日：2002-01-24

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： H03M166

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

摘要翻译： 提供具有小面积的D / A转换电路。 在D / A转换电路中，根据从地址解码器的地址线发送的数字信号，选择四个灰度电压线中的一个。 包括两个N沟道TFT的电路串联连接到包括两个P沟道TFT的电路，并且包括彼此串联连接的电路的电路并联连接到每个灰度电压线。 此外，包括两个N沟道TFT的电路和包括两个P沟道TFT的电路的布置对于每个灰度电压线都是反向的。 由此，D / A转换电路中的布线的交叉变小，可以使面积变小。

公开(公告)号：US20050219098A1

公开(公告)日：2005-10-06

申请号：US11128333

申请日：2005-05-13

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： G09G3/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H03K17/687 ,  H03K17/693 ,  H03M1/66 ,  H03M1/68 ,  H03M1/76

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

公开(公告)号：US07184017B2

公开(公告)日：2007-02-27

申请号：US11128333

申请日：2005-05-13

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： G09G3/36

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

摘要翻译： 提供具有小面积的D / A转换电路。 在D / A转换电路中，根据从地址解码器的地址线发送的数字信号，选择四个灰度电压线中的一个。 包括两个N沟道TFT的电路串联连接到包括两个P沟道TFT的电路，并且包括彼此串联连接的电路的电路并联连接到每个灰度电压线。 此外，包括两个N沟道TFT的电路和包括两个P沟道TFT的电路的布置对于每个灰度电压线都是反向的。 由此，D / A转换电路中的布线的交叉变小，可以使面积变小。

公开(公告)号：US06911926B2

公开(公告)日：2005-06-28

申请号：US10810573

申请日：2004-03-29

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： G09G3/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/04 ,  H03K17/687 ,  H03K17/693 ,  H03M1/66 ,  H03M1/68 ,  H03M1/76 ,  H03M1/00

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

摘要翻译： 提供具有小面积的D / A转换电路。 在D / A转换电路中，根据从地址解码器的地址线发送的数字信号，选择四个灰度电压线中的一个。 包括两个N沟道TFT的电路串联连接到包括两个P沟道TFT的电路，并且包括彼此串联连接的电路的电路并联连接到每个灰度电压线。 此外，包括两个N沟道TFT的电路和包括两个P沟道TFT的电路的布置对于每个灰度电压线都是反向的。 由此，D / A转换电路中的布线的交叉变小，可以使面积变小。

公开(公告)号：US06441758B1

公开(公告)日：2002-08-27

申请号：US09197766

申请日：1998-11-23

申请人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

发明人： Jun Koyama ,  Mitsuaki Osame ,  Yukio Tanaka ,  Munehiro Azami ,  Naoko Yano ,  Shou Nagao

IPC分类号： H03M100

CPC分类号： H01L27/1214 ,  G09G3/20 ,  G09G3/2011 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0218 ,  G09G2310/027 ,  G09G2310/0297 ,  H01L21/84 ,  H01L29/04 ,  H03K17/6872 ,  H03K17/693 ,  H03M1/682 ,  H03M1/765

摘要： A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

摘要翻译： 提供具有小面积的D / A转换电路。 在D / A转换电路中，根据从地址解码器的地址线发送的数字信号，选择四个灰度电压线中的一个。 包括两个N沟道TFT的电路串联连接到包括两个P沟道TFT的电路，并且包括彼此串联连接的电路的电路并联连接到每个灰度电压线。 此外，包括两个N沟道TFT的电路和包括两个P沟道TFT的电路的布置对于每个灰度电压线都是反向的。 由此，D / A转换电路中的布线的交叉变小，可以使面积变小。