公开(公告)号：US5731727A

公开(公告)日：1998-03-24

申请号：US527968

申请日：1995-09-14

申请人： Hisashi Iwamoto ,  Yasuhiro Konishi

发明人： Hisashi Iwamoto ,  Yasuhiro Konishi

IPC分类号： G11C11/407 ,  G11C11/4076 ,  H03K5/13 ,  H03K19/096 ,  H03L7/081 ,  H03K5/14 ,  H03L1/00

CPC分类号： H03L7/081 ,  H03K5/133

摘要： A control transistor is connected in parallel with an input transistor of a bias generation circuit in a voltage control delay circuit. A power supply potential Vcc is divided by voltage divider resistors to be applied to the gate of the control transistor. Reduction in the power supply potential Vcc causes reduction in a current Ib flowing to the control transistor, and a current Ic=Ia+Ib flowing to a delay time variable element. When the power supply potential Vcc is reduced, the factor of a delay time period of delay time variable elements becoming shorter due to a smaller amplitude of a clock signal is canceled with the factor of the delay time period of the delay time variable elements become longer due to a smaller current Ic flowing thereto. Therefore, variation in the delay time period can be suppressed to a low level.

摘要翻译： 控制晶体管与电压控制延迟电路中的偏置产生电路的输入晶体管并联连接。 电源电位Vcc由施加到控制晶体管的栅极的分压电阻器分压。 电源电位Vcc的降低导致流向控制晶体管的电流Ib的减少，流入延迟时间可变元件的电流Ic = Ia + Ib。 当电源电位Vcc减小时，延迟时间可变元件由于时钟信号的较小振幅而变短的延迟时间的因子被延迟时间可变元件的延迟时间的因数变得更长 由于流过其的较小的电流Ic。 因此，可以将延迟时间段的变化抑制到低水平。

公开(公告)号：US5592434A

公开(公告)日：1997-01-07

申请号：US548285

申请日：1995-10-25

申请人： Hisashi Iwamoto ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Yasumitsu Murai

发明人： Hisashi Iwamoto ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Yasumitsu Murai

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/1048 ,  G11C7/1072

摘要： To one memory array, global signal input/output line pairs in two systems, a switch for connecting the global IO line pairs to a write buffer group alternately on a clock cycle basis, and another switch for connecting the global IO line pairs to an equalize circuit alternately on a clock cycle basis are provided. During one clock cycle, writing of data through one global IO line pair and equalization of the other global IO line pair can be carried out in parallel. Therefore, data can be written easily at a high frequency.

摘要翻译： 对于一个存储器阵列，两个系统中的全局信号输入/输出线对，用于以时钟周期交替地将全局IO线对连接到写缓冲器组的开关，以及用于将全局IO线对连接到等于 提供了基于时钟周期的交替电路。 在一个时钟周期内，可以并行执行通过一个全局IO线对写入数据和对另一个全局IO线对进行均衡。 因此，可以高频地容易地写入数据。

公开(公告)号：US5587950A

公开(公告)日：1996-12-24

申请号：US461907

申请日：1995-06-05

申请人： Seiji Sawada ,  Yasuhiro Konishi

发明人： Seiji Sawada ,  Yasuhiro Konishi

IPC分类号： G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/26 ,  G11C29/34 ,  G11C29/40 ,  G11C7/00

CPC分类号： G11C29/40 ,  G11C29/26

摘要： In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression circuit of either a bank #A or a bank #B. A tristate inverter buffer passes the 1-bit compression data selected by the bank selection circuit in accordance with a test mode command signal. The data output terminal outputs compressed data of a plurality of bits of memory cells. Thus, it is possible to simultaneously determine pass/fail of a plurality of memory cells, thereby reducing the test time.

公开(公告)号：US5471430A

公开(公告)日：1995-11-28

申请号：US245784

申请日：1994-05-19

申请人： Seiji Sawada ,  Yasuhiro Konishi

发明人： Seiji Sawada ,  Yasuhiro Konishi

IPC分类号： G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/409 ,  G11C29/00 ,  G11C29/02 ,  G11C29/08 ,  G11C11/34

CPC分类号： G11C29/02 ,  G11C11/406

摘要： A synchronous semiconductor memory device includes an automatic refresh detection circuit for detecting that an automatic refresh mode is specified in accordance with an automatic refresh command, an address counter for generating a refresh address, a refresh execution unit for refreshing a memory array in accordance with an automatic refresh detection signal and the refresh address, an inactivation circuit for inactivating the refresh execution unit after a lapse of a prescribed time in accordance with the automatic refresh detection signal, a counter check mode detection circuit for bringing the inactivation circuit into an inoperable state in accordance with a counter check mode command, and a second inactivation circuit for inactivating the refresh execution unit in accordance with a precharge detection signal generated in response to a precharge command. Thus synchronous semiconductor memory device with an operation mode which can test the function of an internal refresh address counter is provided.

摘要翻译： 同步半导体存储器件包括自动刷新检测电路，用于检测根据自动刷新命令指定自动刷新模式，用于产生刷新地址的地址计数器，用于根据存储器阵列刷新存储器阵列的刷新执行单元 自动刷新检测信号和刷新地址，用于根据自动刷新检测信号在经过规定时间之后使刷新执行单元失活的灭活电路，用于使灭活电路处于不可操作状态的计数器检查模式检测电路 根据计数器检查模式命令，以及第二失活电路，用于根据预充电命令产生的预充电检测信号，使刷新执行单元失效。 因此，提供了具有可以测试内部刷新地址计数器的功能的操作模式的同步半导体存储器件。

公开(公告)号：US5359215A

公开(公告)日：1994-10-25

申请号：US795865

申请日：1991-11-22

申请人： Yasuhiro Konishi

发明人： Yasuhiro Konishi

IPC分类号： G11C11/402 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10808

摘要： A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.

摘要翻译： DRAM包括在P型半导体衬底的主表面上形成的N型阱，形成在P型半导体衬底的主表面上的N型杂质区，形成在N型杂质区中的N型杂质区 型是存储电容器的存储节点，以及用于连接P型杂质区域和N型杂质区域的多晶硅层。 N型杂质层，P型杂质层和多晶硅层构成存储电容器的存储节点，并且从衬底流到N型杂质层的少数载流子的电子与从 N型阱到P型杂质层。