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公开(公告)号：US08417835B2
公开(公告)日：2013-04-09
申请号：US12754481
申请日：2010-04-05
CPC分类号： H04L12/42
摘要： There is provided an apparatus including a plurality of modules. Each module includes a storage unit configured to store a waiting ID and a specific ID of the module, a communication unit configured to transmit and receive packets to and from a bus, and a processing unit configured to process data of a packet which includes a valid flag indicating that the packet is valid, wherein the communication unit takes in data held by a packet which has an ID that coincides with the waiting ID, and stores the processed data in a packet which includes the valid flag indicating invalid and an ID coincident with the specific ID, and transmits the packet.
摘要翻译： 提供了包括多个模块的装置。 每个模块包括存储单元，其被配置为存储模块的等待ID和特定ID，通信单元，被配置为向总线发送和从总线接收分组;以及处理单元，被配置为处理包括有效的分组的数据 指示分组有效的标志，其中通信单元接收由具有与等待ID一致的ID的分组所持有的数据，并将处理的数据存储在包括指示无效的有效标志和与 具体的ID，并发送分组。
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公开(公告)号：US20130013838A1
公开(公告)日：2013-01-10
申请号：US13619603
申请日：2012-09-14
申请人： Isao Sakamoto , Hisashi Ishikawa
发明人： Isao Sakamoto , Hisashi Ishikawa
IPC分类号： G06F13/36
CPC分类号： G06F15/8015 , H04L12/4637 , H04L47/10
摘要： An information processing apparatus includes a plurality of modules connected in a ring shape via a bus, and each module processes a packet flowing in a single direction on the ring in a predetermined order. The module includes a communication unit for transmitting a packet received from a first direction in the ring via the bus to a second direction, a discrimination unit for discriminating a packet from among the packets received from the first direction as a processing packet to be processed by the module, and a processing unit which is connected with the communication unit one by one and configured to process the processing packet. The communication unit transmits the packet processed by the processing unit at an interval equivalent to processing time or more for a processing packet processed by a module in a latter stage in the predetermined order among packets transmitted by the communication unit to the second direction.
摘要翻译： 信息处理装置包括经由总线连接成环状的多个模块，并且每个模块以预定顺序处理环上沿单个方向流动的分组。 该模块包括通信单元，用于经由总线将从环中的第一方向接收到的分组发送到第二方向;识别单元，用于将从第一方向接收的分组中的分组识别为要由第一方向处理的处理分组， 所述模块和处理单元，所述处理单元一个接一个地连接到所述通信单元，并且被配置为处理所述处理分组。 通信单元以对于由通信单元向第二方向发送的分组之间的预定顺序的后级中的模块处理的处理分组，以等于处理时间以上的处理时间间隔处理由处理单元处理的分组。
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公开(公告)号：US20120250090A1
公开(公告)日：2012-10-04
申请号：US13494192
申请日：2012-06-12
申请人： Kenta Hosaki , Hisashi Ishikawa
发明人： Kenta Hosaki , Hisashi Ishikawa
IPC分类号： G06K15/02
CPC分类号： H04N1/32561 , G06T1/00 , G06T2210/32 , H04N1/32101 , H04N2201/3222
摘要： An apparatus for executing image processing by a plurality of serially connected image processing modules stores, in memory, set values for the plurality of image processing modules and image data to be processed by the plurality of image processing modules, adds headers to respective ones of the set values and image data that have been read out of the memory and transmits the result to a top image processing module among the plurality of image processing modules.
摘要翻译： 用于执行多个串行连接的图像处理模块的图像处理的装置在存储器中存储多个图像处理模块的设定值和由多个图像处理模块处理的图像数据，将标题添加到 设置已经从存储器读出的值和图像数据，并将结果发送到多个图像处理模块中的顶部图像处理模块。
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公开(公告)号：US20120219237A1
公开(公告)日：2012-08-30
申请号：US13462048
申请日：2012-05-02
IPC分类号： G06K9/36
CPC分类号： H04N1/32358 , H04N1/193 , H04N1/32443 , H04N1/32475 , H04N2201/0081 , H04N2201/0082 , H04N2201/0091 , H04N2201/3294
摘要： An image data combining apparatus combines m lines of image data that have been output from a reading unit. The reading unit outputs m lines of image data based upon the pixel data that has been output upon being divided into the plurality of lines, and stored then in a memory. An upper address for accessing the memory is decided based upon first data indicating position, along the sub-scan direction, of an image that has been read by the reading unit, and a lower address for accessing the memory is decided based upon second data indicating position of the image along the main-scan direction. For the lower address utilizes values in which the sequence of a plurality of bits constituting the first data is interchanged, so that p items of pixel data at a time are extracted successively from each of the m lines of image data.
摘要翻译： 图像数据组合装置组合从读取单元输出的m行图像数据。 读取单元基于已经被分成多行输出的像素数据输出m行图像数据，然后存储在存储器中。 用于访问存储器的上部地址基于指示沿着副扫描方向的位置，由读取单元读取的图像的位置的第一数据，并且基于第二数据指示 图像沿主扫描方向的位置。 对于较低地址，利用构成第一数据的多个位的序列互换的值，从而从m个图像数据中的每一行连续地提取p个像素数据。
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公开(公告)号：US08243084B2
公开(公告)日：2012-08-14
申请号：US13206766
申请日：2011-08-10
申请人： Hisashi Ishikawa
发明人： Hisashi Ishikawa
IPC分类号： G06F15/80
摘要： A data processing apparatus includes a plurality of processing units each performing a respective one of process parts into which a predetermined process to be performed on data is divided, and a changing unit that changes a connection between the plurality of processing units on the basis of setting parameters that are set to enable a plurality of types of processing procedures.
摘要翻译： 数据处理装置包括多个处理单元，每个处理单元执行对数据执行的预定处理进行划分的处理部分中的相应一个;以及改变单元，其基于设置改变多个处理单元之间的连接 被设置为启用多种类型的处理过程的参数。
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公开(公告)号：US08194279B2
公开(公告)日：2012-06-05
申请号：US12108582
申请日：2008-04-24
CPC分类号： H04N1/32358 , H04N1/193 , H04N1/32443 , H04N1/32475 , H04N2201/0081 , H04N2201/0082 , H04N2201/0091 , H04N2201/3294
摘要： An image data combining apparatus combines m lines of image data that have been output from a reading unit. The reading unit outputs m lines of image data based upon the pixel data that has been output upon being divided into the plurality of lines, and stored then in a memory. An upper address for accessing the memory is decided based upon first data indicating position, along the sub-scan direction, of an image that has been read by the reading unit, and a lower address for accessing the memory is decided based upon second data indicating position of the image along the main-scan direction. For the lower address utilizes values in which the sequence of a plurality of bits constituting the first data is interchanged, so that p items of pixel data at a time are extracted successively from each of the m lines of image data.
摘要翻译： 图像数据组合装置组合从读取单元输出的m行图像数据。 读取单元基于已经被分成多行输出的像素数据输出m行图像数据，然后存储在存储器中。 用于访问存储器的上部地址基于指示沿着副扫描方向的位置，由读取单元读取的图像的位置的第一数据，并且基于第二数据指示 图像沿主扫描方向的位置。 对于较低地址，利用构成第一数据的多个位的序列互换的值，从而从m个图像数据中的每一行连续地提取p个像素数据。
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公开(公告)号：US08156408B2
公开(公告)日：2012-04-10
申请号：US12605048
申请日：2009-10-23
IPC分类号： G06F11/00
摘要： A decoding apparatus acquires, from encoded data, a piece of additional bits that have been partly cut off, acquires, from the piece of the additional bits, the number of bits that are missing due to the cutting off as the number of missing bits, and restores the additional bits by reproducing the missing bits.
摘要翻译： 解码装置从编码数据中获取已被部分切断的附加比特的一部分，从附加比特中获取由于切断的丢失比特数而丢失的比特数， 并通过再现丢失位来恢复附加位。
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98.发明授权Image processing apparatus, image forming apparatus, and control method thereof, which form an image by applying N-ary processing 有权图像处理装置，图像形成装置及其控制方法，其通过应用N元处理形成图像公开(公告)号：US08130415B2
公开(公告)日：2012-03-06
申请号：US13102285
申请日：2011-05-06
CPC分类号： G06K15/107 , H04N1/1911 , H04N1/1915 , H04N1/4053 , H04N1/4092 , H04N1/52
摘要： In order to form a high-quality image, upon execution of multi-pass printing using a printing head with a plurality of nozzles, an image processing apparatus calculates, using a scan duty setting unit, scan duty data for respective nozzles for each scan of the printing head in accordance with input image data. A halftone processor generates a dot pattern to be formed by applying N-ary processing based on predetermined constraining condition information to the calculated scan duty data. A constraining, condition information calculation unit generates constraining condition information to be referred to by the halftone processor at the time of the next scan. The constraining condition information is set so that the phase of a next dot pattern to be generated has an opposite phase relationship in a low frequency region with respect, to the already printed dot pattern.
摘要翻译： 为了形成高质量的图像，在使用具有多个喷嘴的打印头执行多次打印时，图像处理装置使用扫描占空比设置单元计算每个扫描的各个喷嘴的扫描占空比数据 打印头根据输入图像数据。 半色调处理器通过将基于预定约束条件信息的N进制处理应用于计算出的扫描占空比数据而产生点形式。 约束条件信息计算单元产生在下次扫描时由半色调处理器参考的约束条件信息。 约束条件信息被设置为使得相对于已经打印的点图案，要生成的下一点图案的相位在低频区域中具有相反的相位关系。
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公开(公告)号：US20110317938A1
公开(公告)日：2011-12-29
申请号：US13153061
申请日：2011-06-03
IPC分类号： G06K9/54
摘要： An image processing apparatus for processing image data by a plurality of pipeline-connected processing modules is provided. The apparatus includes a first pipeline processing unit configured to include a plurality of processing modules including a processing module which processes image data for every first size; and a second pipeline processing unit configured to be branched from the first pipeline processing unit and include a plurality of processing modules including a processing module which processes image data for every second size different from the first size. The second pipeline processing unit includes, at a start, a change unit configured to acquire partial image data of the first size from the first pipeline processing unit and change the partial image data of the first size into partial image data of the second size.
摘要翻译： 提供了一种用于通过多个流水线连接的处理模块来处理图像数据的图像处理装置。 所述装置包括：第一流水线处理单元，被配置为包括多个处理模块，所述多个处理模块包括处理模块，所述处理模块处理每个第一大小的图像数据; 以及第二流水线处理单元，被配置为从所述第一流水线处理单元分支并且包括多个处理模块，所述多个处理模块包括处理模块，所述处理模块处理与所述第一尺寸不同的每第二尺寸的图像数据。 第二流水线处理单元一开始就包括一个改变单元，其被配置为从第一流水线处理单元获取第一尺寸的部分图像数据，并将第一尺寸的部分图像数据改变为第二尺寸的部分图像数据。
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公开(公告)号：US08086776B2
公开(公告)日：2011-12-27
申请号：US11378005
申请日：2006-03-17
申请人： Hisashi Ishikawa
发明人： Hisashi Ishikawa
CPC分类号： G06F13/364
摘要： In an information-processing apparatus including a plurality of modules and a first arbiter which arbitrates bus-access requests of the plurality of modules, at least one of the plurality of modules includes a plurality of submodules and a second arbiter which arbitrates bus-access requests of the plurality of submodules and transmits at least one of the bus-access requests of the plurality of submodules to the first arbiter. The first arbiter gives priority to the module which transmits many bus-access requests, or the module which made a previous bus access, and limits the number of consecutive accesses made by the same module, so as to control the priority of accessing the bus by the plurality of modules. The second arbiter controls priority of accessing the bus by the plurality of submodules according to the free state of a buffer of each submodule, or the access type, whereby the bus-access requests made by the plurality of modules can be arbitrated, thus increasing bus-use efficiency.
摘要翻译： 在包括多个模块的信息处理装置和仲裁多个模块的总线访问请求的第一仲裁器中，多个模块中的至少一个模块包括多个子模块和仲裁总线访问请求的第二仲裁器 并且将多个子模块的总线访问请求中的至少一个发送到第一仲裁器。 第一个仲裁器优先考虑传输许多总线访问请求的模块，或者进行先前总线访问的模块，并限制同一模块进行的连续访问次数，以便控制访问总线的优先级 多个模块。 第二仲裁器根据每个子模块的缓冲器的自由状态或访问类型来控制由多个子模块访问总线的优先级，从而可以对由多个模块进行的总线访问请求进行仲裁，从而增加总线 利用效率
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