公开(公告)号：US06339355B1

公开(公告)日：2002-01-15

申请号：US09461381

申请日：1999-12-15

申请人： Hiroyuki Yamauchi ,  Yutaka Terada

发明人： Hiroyuki Yamauchi ,  Yutaka Terada

IPC分类号： H03L500

CPC分类号： H03F3/45717

摘要： An offsetting comparator device includes master and slave comparator circuits and a reference differential voltage generator. The master comparator circuit supplies a sensed current corresponding to a potential difference represented by a differential signal on a transmission line. The reference differential voltage generator generates a reference differential voltage based on an intermediate potential of the differential signal. And the slave comparator circuit supplies a current corresponding to the potential difference as offset current. The offsetting comparator device outputs a differential current between the sensed and offset currents and therefore shows an offset in its input/output characteristics. The master and slave comparator circuits have the same circuit configuration. Thus, if the characteristic of the sensed current output from the master comparator circuit has changed due to a potential level variation of the differential signal, then the characteristic of the offset current also changes similarly. Thus, the offsetting comparator device can obtain a constant offset voltage even if the potential level of the differential signal has changed.

摘要翻译： 偏置比较器装置包括主比较器电路和参考差分电压发生器。 主比较器电路在传输线上提供与由差分信号表示的电位差相对应的感测电流。 参考差分电压发生器基于差分信号的中间电位产生参考差分电压。 并且从比较器电路提供对应于电位差的电流作为偏移电流。 偏移比较器装置在感测和偏移电流之间输出差分电流，因此在其输入/输出特性中显示偏移。 主从比较器电路具有相同的电路配置。 因此，如果从主比较器电路输出的检测电流的特性由于差分信号的电位电平变化而改变，则偏移电流的特性也发生类似变化。 因此，即使差分信号的电位电平已经改变，偏移比较器装置也可获得恒定的偏移电压。

公开(公告)号：US06297675B1

公开(公告)日：2001-10-02

申请号：US09478530

申请日：2000-01-06

申请人： Hironori Akamatsu ,  Yutaka Terada ,  Takashi Hirata ,  Yukio Arima ,  Satoshi Takahashi ,  Tadahiro Yoshida ,  Yoshihide Komatsu ,  Hiroyuki Yamauchi

发明人： Hironori Akamatsu ,  Yutaka Terada ,  Takashi Hirata ,  Yukio Arima ,  Satoshi Takahashi ,  Tadahiro Yoshida ,  Yoshihide Komatsu ,  Hiroyuki Yamauchi

IPC分类号： H03B100

CPC分类号： H03K19/018514 ,  Y10T307/549

摘要： A data line pair and a strobe line pair are provided between first and second chips to exchange data therebetween. The first chip includes an output circuit and a controller for controlling the output circuit. The second chip includes an input circuit. For example, the output circuit supplies a direct current from a power supply to one of the data lines. Then, the input circuit feeds back the received current to the output circuit through a pair of terminal resistors and the other data line. Subsequently, the output circuit supplies the fed back direct current to one of the strobe lines. In response, the input circuit feeds back the received current again to the output circuit through another pair of terminal resistors and the other strobe line. And then the fed back current is drained to the ground. Thus, compared to driving the data and strobe line pairs separately with the same amount of current supplied, the current dissipation can be halved. In this manner, the present invention is applicable to reduction of current dissipation when data should be transmitted at high speeds through multiple data bus pairs that are driven with a current supplied.

摘要翻译： 在第一和第二芯片之间提供数据线对和选通线对，以在它们之间交换数据。 第一芯片包括输出电路和用于控制输出电路的控制器。 第二芯片包括输入电路。 例如，输出电路将电流从电源提供给数据线之一。 然后，输入电路通过一对端子电阻和另一条数据线将接收的电流反馈到输出电路。 随后，输出电路将反馈的直流电流提供给选通线之一。 作为响应，输入电路通过另一对端子电阻器和另一个选通线路将接收到的电流再次反馈到输出电路。 然后将反馈电流排到地面。 因此，与以相同的电流量驱动数据和选通线对相比，电流消耗可以减半。 以这种方式，本发明可应用于当通过以所提供的电流驱动的多个数据总线对以高速传输数据时，减少电流消耗。

公开(公告)号：US06055276A

公开(公告)日：2000-04-25

申请号：US538858

申请日：1995-10-04

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H04B3/02 ,  H04L25/08

CPC分类号： H04B3/02 ,  H04L25/08

摘要： In the early half of one period of a main clock, one multiplexer selects a signal Ain, while the other multiplexer selects an inverted signal /Ain. Consequently, the signal Ain is transmitted to a signal line assigned to the signal line Ain, while the signal /Ain is transmitted to a signal line assigned to a signal Bin, thereby accomplishing differential transmission of the signal Ain. In the late half of one period of the main clock, the above one multiplexer selects an inverted signal /Bin, while the above other multiplexer selects the signal Bin. Consequently, the inverted signal /Bin is transmitted to the signal line assigned to the signal Ain, while the signal Bin is transmitted to the signal line assigned to the signal Bin, thereby accomplishing differential transmission of the signal Bin. Since differential transmission is thus accomplished with no increase in the number of wires, power saving can be achieved by data transfer with a small amplitude.

摘要翻译： 在主时钟的一个周期的早半时期，一个多路复用器选择信号Ain，而另一个多路复用器选择反相信号/ Ain。 因此，信号Ain被发送到分配给信号线Ain的信号线，而信号Ain被发送到分配给信号Bin的信号线，从而实现信号Ain的差分传输。 在主时钟的一个周期的后半段中，上述一个多路复用器选择反相信号/ Bin，而上述另一个多路复用器选择信号Bin。 因此，将反相信号/ Bin发送到分配给信号Ain的信号线，同时信号Bin被发送到分配给信号Bin的信号线，从而实现信号Bin的差分传输。 由于差分传输是通过不增加导线来实现的，因此可以通过小振幅的数据传输实现功率节省。

公开(公告)号：US6037816A

公开(公告)日：2000-03-14

申请号：US292381

申请日：1999-04-15

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H03K19/00 ,  H04L25/02 ,  H03K3/356

CPC分类号： H04L25/0292 ,  H04L25/0272 ,  H04L25/028

摘要： In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors. Accordingly, the signal receiving circuit composed of the inverting circuit operates statically in response to the first and second pairs of differential signals.

摘要翻译： 在基于电源电位传输具有极小振幅电压的第一对差分时钟信号UCLK，基于电源电位具有极小幅度电压的第二对差分时钟信号LCLK，LXCLK时， 作为信号接收电路的反相电路由CMOS反相电路构成。 构成CMOS反相电路的PMOS晶体管具有接收第一对差分时钟信号的栅电极和源电极。 构成CMOS反相电路的NMOS晶体管具有接收第二对差分时钟信号的栅电极和源电极。 当差分时钟信号的电位发生变化时，两个晶体管的各个栅极和源极之间的电位在相反的方向上移动，这确实切断晶体管。 因此，由反相电路构成的信号接收电路根据第一和第二对差分信号静态工作。

公开(公告)号：US6028455A

公开(公告)日：2000-02-22

申请号：US994128

申请日：1997-12-19

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H03K19/00 ,  H04L25/02 ,  G01R19/00

CPC分类号： H04L25/0292 ,  H04L25/0272 ,  H04L25/028

摘要： In transmitting a first pair of differential clock signals UCLK, UXCLK having an extremely small amplitude voltage based on a power-source potential and a second pair of differential clock signals LCLK, LXCLK having an extremely small amplitude voltage based on the power-source potential, an inverting circuit as a signal receiving circuit is composed of a CMOS inverting circuit. A PMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the first pair of differential clock signals. An NMOS transistor composing the CMOS inverting circuit has a gate electrode and a source electrode receiving the second pair of differential clock signals. When the potentials of the differential clock signals change, potentials at the respective gate and source electrodes of the two transistors shift in opposite directions, which surely cuts off the transistors. Accordingly, the signal receiving circuit composed of the inverting circuit operates statically in response to the first and second pairs of differential signals.

公开(公告)号：US5898735A

公开(公告)日：1999-04-27

申请号：US726225

申请日：1996-10-04

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H04L25/02 ,  H04L27/04 ,  H04L27/12 ,  H04L27/20

CPC分类号： H04L25/028 ,  H04L25/0272

摘要： Two multiplexors select a first signal Ain and its inverted signal /Ain in the first half of a single cycle of a clock signal and Ain and /Ain, i.e., a differential signal pair, are differential-transmitted to two signal lines. On the other hand, the two multiplexors select a second signal Bin and its inverted signal /Bin in the second half and Bin and /Bin, i.e., a differential signal pair, are differential-transmitted to the two signal lines. Based on the transition probability of Ain and Bin or based on the mode information of a system, either Ain or Bin is selected and is differential-transmitted. As a result of such arrangement, when the transmission of one of Ain and Bin is not required, the other signal can continuously be differential-transmitted using an unoccupied signal line, which makes it possible to increase the rate of signal transmission without having to increase the number of signal lines.

摘要翻译： 两个多路复用器在时钟信号的单个周期的前半部分和Ain和/ Ain（即差分信号对）中选择第一信号Ain及其反相信号/ Ain，差分发送到两条信号线。 另一方面，两个多路复用器选择第二信号Bin，并且其后半部分的反相信号/ Bin和Bin和/ Bin即差分信号对被差分发送到两条信号线。 基于Ain和Bin的转换概率，或者基于系统的模式信息，选择Ain或Bin进行差分发送。 作为这种安排的结果，当不需要Ain和Bin之一的传输时，可以使用未占用的信号线连续地进行差分发送，这使得可以增加信号传输的速率而不必增加 信号线的数量。

公开(公告)号：US5859546A

公开(公告)日：1999-01-12

申请号：US744807

申请日：1996-11-06

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： H03K19/00 ,  H03K19/096

CPC分类号： H03K19/00 ,  H03K19/096

摘要： An exclusive OR circuit is provided which detects whether or not a preceding-stage logical output value and a subsequent-stage logical output value agree. When these logical output values are found to agree, a NAND circuit functions to cut off the supply of a clock signal to a first and second switch circuits and to a latch circuit. Accordingly, when there occur no data changes between clock signal cycles, in a switch circuit and a latch circuit both arranged between each stage of a pipeline, the charge/discharge of the capacitance of gate electrodes of transistors forming these circuits is prevented, thereby reducing power consumption.

摘要翻译： 提供异或电路，其检测前级逻辑输出值和后级逻辑输出值是否一致。 当发现这些逻辑输出值一致时，NAND电路用于切断对第一和第二开关电路和锁存电路的时钟信号的供应。 因此，当在时钟信号周期之间没有发生数据变化时，在开关电路和两个布置在管线的每一级之间的锁存电路中，防止形成这些电路的晶体管的栅电极的电容的充电/放电，从而减少 能量消耗。

公开(公告)号：US5852380A

公开(公告)日：1998-12-22

申请号：US731437

申请日：1996-10-15

申请人： Hiroyuki Yamauchi

发明人： Hiroyuki Yamauchi

IPC分类号： G06F1/10 ,  H03K5/13 ,  H03K5/15 ,  H03L7/081 ,  H03K5/26

CPC分类号： H03K5/1508 ,  G06F1/10 ,  H03K5/133 ,  H03L7/0814

摘要： A phase adjusting circuit includes a circuit for providing an internal clock signal in synchronization with a reference clock signal, a delay circuit for delaying the internal clock signal for a predetermined delay time and an adjusting section for adjusting a phase difference between a phase of the reference clock signal and a phase of the internal clock signal delayed for the predetermined delay time.

摘要翻译： 相位调整电路包括用于与基准时钟信号同步地提供内部时钟信号的电路，用于将内部时钟信号延迟预定延迟时间的延迟电路和用于调整参考时钟相位之间的相位差的调整部分 时钟信号和内部时钟信号的相位延迟了预定的延迟时间。

公开(公告)号：US5835952A

公开(公告)日：1998-11-10

申请号：US808938

申请日：1997-02-28

申请人： Hiroyuki Yamauchi ,  Kazuhiro Matsuyama

发明人： Hiroyuki Yamauchi ,  Kazuhiro Matsuyama

IPC分类号： G06F12/06 ,  G09G5/39 ,  G09G5/399 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C11/00

CPC分类号： G11C11/005 ,  G06F12/0607 ,  G09G5/399 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22

摘要： An image data memory with a 2-bank (bank A and bank B) structure is disclosed. The bank A stores only even field data, whereas the bank B stores only odd field data, and a peripheral circuit composed of elements such as row decoders and column decoders is provided in such a manner that each bank can be accessed independently of the other. One of the banks A and B is precharged while the other bank is accessed in order that the banks A and B are alternately accessed. Fast frame access is accomplished.

摘要翻译： 公开了一种具有2岸（银行A和银行B）结构的图像数据存储器。 存储体A只存储偶数场数据，而存储体B仅存储奇数场数据，并且以这样的方式提供由诸如行解码器和列解码器的元件组成的外围电路，使得可以独立于另一个存取存储体。 银行A和B之一被预先充电，而另一个银行被访问，以便银行A和B被交替访问。 完成快速帧访问。

公开(公告)号：US5715191A

公开(公告)日：1998-02-03

申请号：US733313

申请日：1996-10-17

申请人： Hiroyuki Yamauchi ,  Toru Iwata

发明人： Hiroyuki Yamauchi ,  Toru Iwata

IPC分类号： G11C11/412 ,  G11C11/413

CPC分类号： G11C11/412

摘要： A memory cell includes a load transistor pair serving as a high data holding element, a drive transistor pair serving as a low data holding element, and an access transistor pair for accessing the high data holding element or the low data holding element. A high data holding potential corresponding to the source potential of the load transistor pair is set at a value larger than a supply potential, and a low data holding potential corresponding to the source potential of the drive transistor pair is set at a value larger than a ground potential. In a read operation, a source potential control line of a selected memory cell is connected with a ground line through a source line switch.

摘要翻译： 存储单元包括用作高数据保持元件的负载晶体管对，用作低数据保持元件的驱动晶体管对，以及用于访问高数据保持元件或低数据保持元件的存取晶体管对。 对应于负载晶体管对的源极电位的高数据保持电位被设置为大于电源电位的值，并且与驱动晶体管对的源极电位相对应的低数据保持电位被设置为大于 地电位。 在读取操作中，所选存储单元的源极电位控制线通过源极线开关与地线连接。