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132 条记录 (耗时 0.031 秒)

    Data transmitter
    1.
    发明授权
    Data transmitter 有权
    数据发送器

    公开(公告)号：US06323756B1

    公开(公告)日：2001-11-27

    申请号：US09486868

    申请日：2000-05-26

    申请人： Takefumi Yoshikawa ,  Toru Iwata ,  Hiroyuki Yamauchi

    发明人： Takefumi Yoshikawa ,  Toru Iwata ,  Hiroyuki Yamauchi

    IPC分类号： H04M1104

    CPC分类号： H03K19/017545 ,  H03K19/0013

    摘要： The data transmission device 1a of the present invention includes a driver 10 for sending data, a receiver 20 for receiving the data sent from the driver 10, a transmission line path 30 for connecting between the driver 10 and the receiver 20, and a variable impedance element 40 having a controllably variable impedance. The variable impedance element 40 is connected to the transmission line path 30. The data transmission line device 1a can reduce power consumption and occurrence of skew.

    摘要翻译： 本发明的数据传输装置1a包括用于发送数据的驱动器10，用于接收从驱动器10发送的数据的接收器20，用于连接驱动器10和接收器20的传输线路径30和可变阻抗 元件40具有可控制的可变阻抗。 可变阻抗元件40连接到传输线路径30.数据传输线设备1a可以降低功耗并产生偏斜。

    Variable delay circuit and phase adjustment circuit
    2.
    发明授权
    Variable delay circuit and phase adjustment circuit 失效
    可变延迟电路和相位调整电路

    公开(公告)号：US06426985B1

    公开(公告)日：2002-07-30

    申请号：US09283888

    申请日：1999-04-01

    申请人： Toru Iwata ,  Hiroyuki Yamauchi

    发明人： Toru Iwata ,  Hiroyuki Yamauchi

    IPC分类号： H04L700

    CPC分类号： H03L7/0814 ,  H03L7/07 ,  H03L7/0818

    摘要： A variable delay circuit includes a plurality of delay circuits for delaying an input signal; and a selection circuit for selecting an output from one of the plurality of delay circuits in accordance with a selection signal. The plurality of delay circuits include a first delay circuit for delaying the input signal by a first delay time period and a second delay circuit for delaying the input signal by a second delay time period which is longer than the first delay time period. The difference between the first delay time period and the second delay time period is shorter than a minimum delay time period which is allowed to be set in the first delay circuit.

    摘要翻译： 可变延迟电路包括用于延迟输入信号的多个延迟电路; 以及选择电路，用于根据选择信号选择多个延迟电路之一的输出。 多个延迟电路包括用于将输入信号延迟第一延迟时间段的第一延迟电路和用于将输入信号延迟比第一延迟时间段长的第二延迟时间段的第二延迟电路。 第一延迟时间段和第二延迟时间段之间的差值比允许在第一延迟电路中设置的最小延迟时间段短。

    Data holding circuit
    5.
    发明授权
    Data holding circuit 失效
    数据保持电路

    公开(公告)号：US5757702A

    公开(公告)日：1998-05-26

    申请号：US739363

    申请日：1996-10-29

    申请人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

    发明人： Toru Iwata ,  Hironori Akamatsu ,  Hiroyuki Yamauchi

    IPC分类号： G11C11/412 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419 ,  G11C11/412

    摘要： A memory cell includes a first inverter and a second inverter connected with each other through the output node of one of the inverters and the input node of the other inverter, and first and second transistors. Each of the transistors connected with a word line at its gate electrode is interposed between one of a bit line pair and each memory node. This data holding circuit includes an element for increasing a memory cell supply potential for driving the pair of inverters to be higher than a supply potential applied to peripheral circuits, or an element for decreasing a ground voltage for driving the pair of inverters to be lower than a ground voltage applied to the peripheral circuits.

    摘要翻译： 存储单元包括通过其中一个反相器的输出节点和另一个反相器的输入节点以及第一和第二晶体管彼此连接的第一反相器和第二反相器。 在其栅电极处与字线连接的晶体管中的每一个插入在位线对和每个存储器节点之一之间。 该数据保持电路包括用于将用于驱动该对反相器的存储单元电源电位增加到高于施加到外围电路的电源电位的元件，或者用于将用于驱动该对反相器的接地电压降低到低于 施加到外围电路的接地电压。

    Clock recovery circuit
    6.
    发明申请
    Clock recovery circuit 审中-公开
    时钟恢复电路

    公开(公告)号：US20070041483A1

    公开(公告)日：2007-02-22

    申请号：US11586587

    申请日：2006-10-26

    申请人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

    发明人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

    IPC分类号： H03D3/24

    CPC分类号： H04L25/45 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H04L7/033

    摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

    摘要翻译： 驱动器和接收器提供数据信号，其基于具有常规位模式的串行数据，例如时钟，其包括在调整周期期间彼此交替的1和0，并且基于具有任意的串行数据 在调整周期后的转移期间的位模式。 占空因数控制器调节驱动器或接收器的数据转换特性，使得从接收器提供的数据信号的占空比在调整周期中等于50％，并且具有被调整的数据转换特性。 时钟恢复单元恢复与在传送时段中从接收器提供的数据信号同步的时钟，并且基于来自数据信号的经调整的转换特性。

    Clock recovery circuit
    7.
    发明授权
    Clock recovery circuit 有权

    公开(公告)号：US07136441B2

    公开(公告)日：2006-11-14

    申请号：US10038613

    申请日：2002-01-08

    申请人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

    发明人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

    IPC分类号： H04L7/00

    CPC分类号： H04L25/45 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H04L7/033

    摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

    Semiconductor device having a plurality of semiconductor chips connected together by a bus
    8.
    发明授权
    Semiconductor device having a plurality of semiconductor chips connected together by a bus 有权
    具有通过总线连接在一起的多个半导体芯片的半导体装置

    公开(公告)号：US06633607B1

    公开(公告)日：2003-10-14

    申请号：US09249695

    申请日：1999-02-12

    申请人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

    发明人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

    IPC分类号： H03K904

    CPC分类号： H03M9/00 ,  H04L25/49

    摘要： A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.

    摘要翻译： 一种半导体器件包括：发送部分; 以及接收部分，其中所述发送部分和所述接收部分通过总线相互连接，所述发送部分包括用于对包括多个比特的数据进行编码的编码部分，以产生指示至少的位置的比特位置信息 从包含在数据中的多个比特中选择一个比特，以及用于将比特位置信息输出到总线上的输出部分，并且接收部分包括用于从总线接收比特位置信息的输入部分和解码 用于解码位位置信息以产生数据。

    Semiconductor memory
    9.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US6009024A

    公开(公告)日：1999-12-28

    申请号：US46880

    申请日：1998-03-24

    申请人： Takashi Hirata ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Satoshi Takahashi ,  Yutaka Terada

    发明人： Takashi Hirata ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Satoshi Takahashi ,  Yutaka Terada

    IPC分类号： G11C7/06 ,  G11C7/00

    CPC分类号： G11C7/06

    摘要： A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.

    摘要翻译： 本发明的半导体存储器包括：多个存储单元; 连接到所述多个存储器单元的一对局部位线; 本地读出放大器，用于放大一对局部位线之间的电位差; 一对全局位线通过开关电连接到该对局部位线; 以及用于放大所述一对全局位线之间的电位差的全局读出放大器，其中所述局部读出放大器包括多个晶体管，所述局部读出放大器中包括的所述多个晶体管中的每一个是第一导电类型的晶体管， 并且全球感测放大器包括不同于第一导电类型的第二导电类型的晶体管。