公开(公告)号：US08456582B2

公开(公告)日：2013-06-04

申请号：US13030133

申请日：2011-02-18

Applicant: Yu-Cheng Chen ,  Yi-Hui Li ,  Chih-Hung Lin ,  Maw-Song Chen

Inventor： Yu-Cheng Chen ,  Yi-Hui Li ,  Chih-Hung Lin ,  Maw-Song Chen

IPC: G02F1/1343

CPC classification number: G02F1/136213 ,  G02F1/133707

Abstract: An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a gate insulating layer, a pixel electrode, a capacitor electrode, and a capacitor dielectric layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The gate insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the gate insulating layer. The capacitor dielectric layer is located between the capacitor electrode and the drain.

Abstract translation: 提供有源器件，像素结构和显示面板。 像素结构包括扫描线，数据线，有源器件，栅极绝缘层，像素电极，电容器电极和电容器电介质层。 有源器件包括栅极，沟道，源极和漏极。 栅极电连接到扫描线。 源电连接到数据线。 栅极绝缘层设置在栅极和沟道之间。 像素电极电连接到漏极。 电容电极位于栅极绝缘层上。 电容器电介质层位于电容器电极和漏极之间。

公开(公告)号：US20130075766A1

公开(公告)日：2013-03-28

申请号：US13448359

申请日：2012-04-16

Applicant: Che-Chia Chang ,  Sheng-Chao Liu ,  Wu-Liu Tsai ,  Chuan-Sheng Wei ,  Chih-Hung Lin

Inventor： Che-Chia Chang ,  Sheng-Chao Liu ,  Wu-Liu Tsai ,  Chuan-Sheng Wei ,  Chih-Hung Lin

IPC: H01L27/15 ,  H01L27/105

CPC classification number: G02F1/136213 ,  G02F1/136286 ,  G09G3/3677 ,  G09G2310/0286 ,  H01L27/1255

Abstract: A thin film transistor device, disposed on a substrate, includes a gate electrode, a semiconductor channel layer, a gate insulating layer disposed between the gate electrode and the semiconductor channel layer, a source electrode and a drain electrode disposed at two opposite sides of the semiconductor channel layer and partially overlapping the semiconductor channel layer, respectively, a capacitor electrode at least partially overlapping the gate electrode, and a capacitor dielectric layer disposed between the capacitor electrode and the gate electrode. The capacitor electrode, the gate electrode and the capacitor dielectric layer form a capacitor device.

Abstract translation: 设置在基板上的薄膜晶体管器件包括栅电极，半导体沟道层，设置在栅电极和半导体沟道层之间的栅极绝缘层，设置在栅极电极和半导体沟道层的两相对侧的源电极和漏电极 半导体沟道层和半导体沟道层的部分重叠，至少部分地与栅电极重叠的电容器电极和设置在电容器电极和栅电极之间的电容器电介质层。 电容器电极，栅极电极和电容器介电层形成电容器器件。

公开(公告)号：US08383480B1

公开(公告)日：2013-02-26

申请号：US13295191

申请日：2011-11-14

Applicant: Chih-Ming Wang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin

Inventor： Chih-Ming Wang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Hsiang-Chen Lee ,  Chih-Hung Lin

IPC: H01L21/336

CPC classification number: H01L29/4234 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: A method for forming a semiconductor structure includes following steps. A substrate structure is provided. The substrate structure includes a semiconductor substrate, a first oxide-nitride-oxide (ONO) layer, and a second ONO layer. The semiconductor substrate has first and second surfaces opposite to each other. The first ONO layer includes a first oxide layer, a first nitride layer and a second oxide layer formed on the first surface in sequence. The second ONO layer includes a third oxide layer, a second nitride layer and a fourth oxide layer formed on the second surface in sequence. A nitride mask layer is formed on the first ONO layer. The fourth oxide layer is removed. The second nitride layer and the nitride mask layer are removed. The second oxide layer and the third oxide layer are removed. A fifth oxide layer is formed on the first nitride layer.

Abstract translation: 一种形成半导体结构的方法包括以下步骤。 提供了基板结构。 衬底结构包括半导体衬底，第一氧化物 - 氧化物 - 氧化物（ONO）层和第二ONO层。 半导体衬底具有彼此相对的第一和第二表面。 第一ONO层包括顺序地形成在第一表面上的第一氧化物层，第一氮化物层和第二氧化物层。 第二ONO层包括依次形成在第二表面上的第三氧化物层，第二氮化物层和第四氧化物层。 在第一ONO层上形成氮化物掩模层。 去除第四氧化物层。 去除第二氮化物层和氮化物掩模层。 去除第二氧化物层和第三氧化物层。 在第一氮化物层上形成第五氧化物层。

公开(公告)号：US20110233567A1

公开(公告)日：2011-09-29

申请号：US12788301

申请日：2010-05-27

Applicant: Yi-Hui Li ,  Yu-Cheng Chen ,  Tsan-Chun Wang ,  Chih-Hung Lin ,  Tung-Huang Chen

Inventor： Yi-Hui Li ,  Yu-Cheng Chen ,  Tsan-Chun Wang ,  Chih-Hung Lin ,  Tung-Huang Chen

IPC: H01L33/00

CPC classification number: H01L27/12 ,  G02F1/136286 ,  G02F2201/40 ,  H01L27/124

Abstract: A pixel array is located on a substrate and includes a plurality of pixel sets. Each of the pixel sets includes a first scan line, a second scan line, a data line, a data signal transmission line, a first pixel unit, and a second pixel unit. The data line is not parallel to the first and the second scan lines. The data signal transmission line is disposed parallel to the first and the second scan lines and electrically connected to the data line. Distance between the first and the second scan lines is smaller than distance between the data signal transmission line and one of the first and the second scan lines. The first pixel unit is electrically connected to the first scan line and the data line. The second pixel unit is electrically connected to the second scan line and the data line.

Abstract translation: 像素阵列位于衬底上并且包括多个像素组。 每个像素组包括第一扫描线，第二扫描线，数据线，数据信号传输线，第一像素单元和第二像素单元。 数据线不平行于第一和第二扫描线。 数据信号传输线平行于第一和第二扫描线设置并与数据线电连接。 第一和第二扫描线之间的距离小于数据信号传输线与第一和第二扫描线之一之间的距离。 第一像素单元电连接到第一扫描线和数据线。 第二像素单元电连接到第二扫描线和数据线。

公开(公告)号：US20100315583A1

公开(公告)日：2010-12-16

申请号：US12788876

申请日：2010-05-27

Applicant: Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

Inventor： Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

IPC: G02F1/1343 ,  H01L21/84

CPC classification number: G02F1/136209 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2201/40 ,  H01L27/1248 ,  H01L27/1255

Abstract: This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

Abstract translation: 本发明在一个方面涉及像素结构。 在一个实施例中，像素结构包括形成在衬底上的扫描线和形成在限定像素区域的衬底上的数据线，形成在衬底上的像素区域内的开关，形成在开关上的屏蔽电极，有机平面 形成在日期线和像素区域上并且与屏蔽电极不重叠的像素电极，以及具有从第一部分延伸的第一部分和第二部分的像素电极，并且形成在屏蔽电极和平面有机层的上方 像素区域，其中第一部分与屏蔽电极重叠以便在其间限定存储电容器，并且第二部分覆盖平面有机层并且不与数据线重叠。

公开(公告)号：US20090147689A1

公开(公告)日：2009-06-11

申请号：US12010841

申请日：2008-01-30

Applicant: Hsin-Chien Kao ,  Jain Shing Wu ,  Chih-Hung Lin

Inventor： Hsin-Chien Kao ,  Jain Shing Wu ,  Chih-Hung Lin

IPC: H04L12/26

CPC classification number: H04L63/1408 ,  H04L43/10

Abstract: Method, network apparatus and computer readable medium thereof for detecting the defect of the network are provided. The network apparatus comprises a controlling module and a relaying module. The controlling module comprises a generating module for generating a plurality of sub-detecting packets; and a first combining module for combining the plurality of sub-detecting module into a detecting packet; the relaying module is for receiving the detecting packet from the controlling module, the relaying module comprises a decomposing module for decomposing the detecting packet into the plurality of sub-detecting packets and transfer the sub-detecting packets to a target host; and a second combining module for receiving a plurality sub-result packets from the target host which are corresponding to the sub-detecting packets, combining the sub-result packets into a result packet and transferring the result packet to the controlling module to complete the detection.

Abstract translation: 提供了用于检测网络缺陷的方法，网络设备及其计算机可读介质。 网络装置包括控制模块和中继模块。 所述控制模块包括用于产生多个子检测分组的生成模块; 以及第一组合模块，用于将所述多个子检测模块组合成检测包; 所述中继模块用于从所述控制模块接收所述检测分组，所述中继模块包括分解模块，用于将所述检测分组分解成所述多个子检测分组，并将所述子检测分组传送到目标主机; 以及第二组合模块，用于从所述目标主机接收对应于所述子检测分组的多个子结果分组，将所述子结果分组组合成结果分组，并将所述结果分组传送到所述控制模块以完成所述检测 。

公开(公告)号：US20080192010A1

公开(公告)日：2008-08-14

申请号：US11757469

申请日：2007-06-04

Applicant: Chih-Hung Lin

Inventor： Chih-Hung Lin

IPC: G06F3/033

CPC classification number: G06F3/0362 ,  G06F3/03543 ,  G06F3/0383

Abstract: The present invention relates to a tilt wheel type mouse. The tilt wheel type mouse includes a tiltable scroll wheel, a switch button and a switching program. Under execution of the switching program, a frame shown on a computer screen is backward to the previous page or forward to the next page when the scroll wheel is rotated in the left or right direction.

Abstract translation: 本发明涉及一种倾斜轮式鼠标。 倾斜轮型鼠标包括可倾斜滚轮，开关按钮和切换程序。 在切换程序的执行下，当滚轮沿左或右方向旋转时，计算机屏幕上所示的帧向后返回到前一页或向前移动到下一页。

公开(公告)号：US20080062130A1

公开(公告)日：2008-03-13

申请号：US11624036

申请日：2007-01-17

Applicant: Chih-Hung Lin

Inventor： Chih-Hung Lin

IPC: G09G5/08

CPC classification number: G06F3/03543

Abstract: A mouse having a hot key is used for performing an internet searching operation. The mouse is electrically connected to a computer system, which is linked to a preset search website including a search box. The mouse includes a hot key and a hot key processing program. The hot key is activated to generate a depressing signal and a release signal. The hot key processing program is executed to be linked to the search website and implement the internet searching operation, wherein at least a search keyword marked by a user is copied in response to the depressing signal, and the computer system is linked to the preset search website and the marked search keyword is pasted into the search box in response to the release signal, thereby implementing the internet searching operation.

Abstract translation: 具有热键的鼠标用于执行因特网搜索操作。 鼠标电连接到计算机系统，其连接到包括搜索框的预设搜索网站。 鼠标包括热键和热键处理程序。 热键被激活以产生按下的信号和释放信号。 执行热键处理程序以链接到搜索网站并实现因特网搜索操作，其中至少响应于按下的信号复制由用户标记的搜索关键字，并且计算机系统链接到预设搜索 网站和标记的搜索关键字被粘贴到搜索框中以响应释放信号，从而实现互联网搜索操作。

公开(公告)号：US20070273439A1

公开(公告)日：2007-11-29

申请号：US11420482

申请日：2006-05-26

Applicant: Chih-Hung Lin ,  Jiunn-Tsair Chen

Inventor： Chih-Hung Lin ,  Jiunn-Tsair Chen

IPC: H03G3/20

CPC classification number: H03F1/3247 ,  H03F2201/3233

Abstract: This invention is about a DAPD-LUT technique of dynamically adapting an LUT spacing for linearizing a power amplifier (PA). It optimizes the LUT spacing for the PA without prior knowledge of system state information. A size-N LUT divides a whole unsaturated PA input amplitude range into N bins, each predistorted by an entry of the LUT. The LUT is indexed by an input amplitude of a modulated signal via an index mapper to implement an unconditionally non-uniform LUT spacing. A spacing adaptor online interactively adapts the LUT spacing. The adapted LUT spacing balances the IMD power at the PA output corresponding to each bin, so that the total IMD power at the PA output is minimized. This dynamically-optimum technique is practical, robust, and with low complexity.

Abstract translation: 本发明涉及动态地适应用于线性化功率放大器（PA）的LUT间隔的DAPD-LUT技术。 它优化了PA的LUT间距，而无需系统状态信息的知识。 尺寸N LUT将整个不饱和PA输入幅度范围划分为N个存储区，每个存储块由LUT的条目预失真。 LUT通过索引映射器的调制信号的输入幅度进行索引，以实现无条件不均匀的LUT间隔。 在线间距适配器交互式地适应LUT间隔。 适应的LUT间隔平衡与每个仓相对应的PA输出处的IMD功率，使得PA输出端的总IMD功率最小化。 这种动态最优的技术是实用的，稳健的，复杂度低的。

公开(公告)号：US20070123049A1

公开(公告)日：2007-05-31

申请号：US11164278

申请日：2005-11-17

Applicant: Kao-Su Huang ,  Ying-Ming Tseng ,  Chia-Hsun Yu ,  Chih-Hung Lin

Inventor： Kao-Su Huang ,  Ying-Ming Tseng ,  Chia-Hsun Yu ,  Chih-Hung Lin

IPC: C23F1/00 ,  H01L21/461 ,  C03C15/00 ,  H01L21/302

CPC classification number: H01L21/28035 ,  H01L21/02071 ,  H01L21/32137

Abstract: A semiconductor process is provided. A substrate is provided and then a to-be-etched layer is formed on the substrate. A patterned photoresist layer is formed on the to-be-etched layer. The to-be-etching layer is etched using a gaseous etchant to form a patterned layer. In the meantime, some of the gaseous etchant is condensed on the patterned photoresist layer and above the substrate after the etching process. Thereafter, a heat treatment process is performed to remove the condensed gaseous etchant. An ion implanting process is performed to form a doped region in the substrate. After the ion implanting process, the patterned photoresist layer is removed.

Abstract translation: 提供半导体工艺。 提供衬底，然后在衬底上形成被蚀刻层。 在被蚀刻层上形成图案化的光致抗蚀剂层。 使用气体蚀刻剂蚀刻待蚀刻层以形成图案化层。 同时，在刻蚀工艺之后，一些气体蚀刻剂在图案化的光致抗蚀剂层上和基板之上被冷凝。 此后，进行热处理工艺以除去冷凝的气态蚀刻剂。 执行离子注入工艺以在衬底中形成掺杂区域。 在离子注入工艺之后，去除图案化的光致抗蚀剂层。