公开(公告)号：US20210407934A1

公开(公告)日：2021-12-30

申请号：US16911543

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Neelam Prabhu Gaunkar ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Diego Correas-Serrano ,  Henning Braunisch

IPC: H01L23/66 ,  H01L23/498 ,  H01P3/00 ,  H01P3/08

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US11133263B2

公开(公告)日：2021-09-28

申请号：US16573948

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Henning Braunisch ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48 ,  H05K1/18

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

公开(公告)号：US11108433B2

公开(公告)日：2021-08-31

申请号：US16206919

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Georgios Dogiamis ,  Jeff C. Morriss ,  Hyung-Jin Lee ,  Richard Dischler ,  Ajay Balankutty ,  Telesphor Kamgaing ,  Said Rami

IPC: H04B3/52 ,  H04L27/36

Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.

公开(公告)号：US11004824B2

公开(公告)日：2021-05-11

申请号：US15389100

申请日：2016-12-22

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Henning Braunisch ,  Javier Soto Gonzalez ,  Shawna M. Liff

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

公开(公告)号：US20210082825A1

公开(公告)日：2021-03-18

申请号：US16573948

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Veronica Strong ,  Aleksandar Aleksov ,  Henning Braunisch ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: H01L23/538 ,  H05K1/18 ,  H01L23/00 ,  H01L25/10 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.

公开(公告)号：US20210080500A1

公开(公告)日：2021-03-18

申请号：US16573946

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Aleksandar Aleksov ,  Veronica Strong ,  Brandon Rawlings ,  Johanna Swan ,  Shawna Liff

IPC: G01R31/28 ,  G01K7/42

Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.

公开(公告)号：US20210074620A1

公开(公告)日：2021-03-11

申请号：US16564168

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Johanna Swan ,  Henning Braunisch ,  Aleksandar Aleksov ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong

IPC: H01L23/498 ,  G03F1/54 ,  G03F1/68 ,  G03F1/38

Abstract: An lithographic reticle may be formed comprising a transparent substrate, a substantially opaque mask formed on the transparent substrate that defines at least one exposure window, wherein the at least one exposure window has a first end, a first filter formed on the transparent substrate within the at least one exposure window and abutting the first end thereof, and a second filter formed on the transparent substrate within the at least one exposure window and abutting the first filter, wherein an average transmissivity of the first filter is substantially one half of a transmissivity of the second filter. In another embodiment, the at least one exposure window includes a third filter abutting the second end and is adjacent the second filter. Further embodiments of the present description include interconnection structures and systems fabricated using the lithographic reticle.

公开(公告)号：US10943851B1

公开(公告)日：2021-03-09

申请号：US16706383

申请日：2019-12-06

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Henning Braunisch ,  Johanna Swan

IPC: H01L23/473 ,  G02B6/122 ,  G02B6/13 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/16 ,  H01L25/00 ,  H01L21/48 ,  H05K1/02

Abstract: An integrated circuit device assembly may be formed comprising a reconstituted wafer attached to a base substrate, wherein the base substrate provides thermal management and optical signal routes. In one embodiment, the base substrate may include a plurality of electrical interconnects for electrically coupling integrated circuit devices in the reconstituted wafer. In another embodiment, a plurality of electrical interconnects for electrically coupling integrated circuit devices in the reconstituted wafer may be formed in the reconstituted wafer itself.

公开(公告)号：US20200303328A1

公开(公告)日：2020-09-24

申请号：US16394537

申请日：2019-04-25

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Adel A. Elsherbini ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Richard Dischler ,  Johanna M. Swan ,  Victor J. Prokoff

IPC: H01L23/66 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.

公开(公告)号：US20200294940A1

公开(公告)日：2020-09-17

申请号：US16397923

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Adel A. Elsherbini ,  Henning Braunisch ,  Johanna M. Swan ,  Telesphor Kamgaing

IPC: H01L23/66 ,  G02B6/30 ,  H01P11/00 ,  H01P3/16

Abstract: Embodiments may relate to a semiconductor package that includes a package substrate coupled with a die. The package may further include a waveguide coupled with the first package substrate. The waveguide may include two or more layers of a dielectric material with a waveguide channel positioned between two layers of the two or more layers of the dielectric material. The waveguide channel may convey an electromagnetic signal with a frequency greater than 30 gigahertz (GHz). Other embodiments may be described or claimed.