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    VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT
    2.
    发明公开
    VARACTOR DEVICE WITH BACKSIDE ELECTRICAL CONTACT 审中-公开

    公开(公告)号：US20230420578A1

    公开(公告)日：2023-12-28

    申请号：US17848660

    申请日：2022-06-24

    申请人： Intel Corporation

    发明人： Ayan Kar ,  Kalyan C. Kolluru ,  Nicholas A. Thomson ,  Vijaya Bhaskara Neeli ,  Said Rami ,  Saurabh Morarka ,  Karthik Krishaswamy ,  Mauro J. Kobrinsky

    IPC分类号： H01L29/93 ,  H01L29/06 ,  H01L29/417

    CPC分类号： H01L29/93 ,  H01L29/0673 ,  H01L29/417 ,  H01L29/42392

    摘要： A varactor device includes a support structure, an electrically conductive layer at the backside of the support structure, two semiconductor structures including doped semiconductor materials, two contact structures, and a semiconductor region. Each contract structure is electrically conductive and is connected to a different one of the semiconductor structures A contract structure couples the corresponding semiconductor structure to the electrically conductive layer. The semiconductor region is between the two semiconductor structures and can be connected to the two semiconductor structures. The semiconductor region may include non-planar semiconductor structures coupled with a gate. The gate may be coupled to another electrically conductive layer at the frontside of the support structure. The varactor device may further include a pair of additional semiconductor regions that are electrically insulated from each other. The additional semiconductor regions may be coupled to two oppositely polarized gates, respectively.

    FIELD-EFFECT TRANSISTORS WITH ASYMMETRIC GATE STACKS
    4.
    发明申请
    FIELD-EFFECT TRANSISTORS WITH ASYMMETRIC GATE STACKS 审中-公开

    公开(公告)号：US20200259018A1

    公开(公告)日：2020-08-13

    申请号：US16270826

    申请日：2019-02-08

    申请人： Intel Corporation

    发明人： Said Rami ,  Hyung-Jin Lee ,  Saurabh Morarka ,  Guannan Liu ,  Qiang Yu ,  Bernhard Sell ,  Mark Armstrong

    IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/40

    摘要： Disclosed herein are field-effect transistors with asymmetric gate stacks. An example transistor includes a channel material and an asymmetric gate stack, provided over a portion of the channel material between source and drain (S/D) regions. The gate stack is asymmetric in that a thickness of a gate dielectric of a portion of the gate stack closer to one of the S/D regions is different from that of a portion of the gate stack closer to the other S/D region, and in that a work function (WF) material of a portion of the gate stack closer to one of the S/D regions is different from a WF material of a portion of the gate stack closer to the other S/D region. Transistors as described herein exploit asymmetry in the gate stacks to improve the transistor performance in terms of high breakdown voltage, high gain, and/or high output resistance.