公开(公告)号：US20210152404A1

公开(公告)日：2021-05-20

申请号：US17127853

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Itamar Levin ,  Tali Warshavsky Grafi ,  Marco Cusmai ,  Ajay Balankutty ,  FNU Shiva Kiran ,  Ariel Cohen

IPC: H04L25/03

Abstract: An apparatus comprising at least one medium to transport a signal and an analog equalization circuit to perform equalization on the signal, wherein the analog equalization circuit comprises independently tunable parameters including a peak frequency gain and a mid-range frequency response slope.

公开(公告)号：US12265483B2

公开(公告)日：2025-04-01

申请号：US17338479

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Sandipan Kundu ,  Jihwan Kim ,  Ajay Balankutty ,  Bong Chan Kim ,  Yutao Liu ,  Frank O'Mahony

IPC: G06F13/42 ,  G06F1/04 ,  G06F13/16 ,  H03K17/687 ,  H03K19/20

Abstract: A clock buffer that uses low-to-medium quality factor (e.g., QF of 2 to 5) inductors in shunt-series and in series-shunt configuration in high-speed clock distribution stages. Shunt-series and series-shunt inductors extend amplifier bandwidth. Applying shunt-series and series-shunt inductors to high-speed clock distribution filters jitter, attenuates supply noise, and improves fanout. An asymmetric multiplexer with inductors in shunt or in shunt-series configurations. Another asymmetric multiplexer with capacitively coupled tri-stateable inverter-based buffer stages. These two multiplexer techniques along with the ability to ‘hide’ a load of a non-preferred path at a virtual ground node of the shunt inductor, the multiplexer improves the jitter and power consumption of the preferred path significantly. A de-multiplexer (DeMux) is also shown using inductors. A combination of a shunt-multiplexer and an inductor-based DeMux is also discussed.

公开(公告)号：US20210320652A1

公开(公告)日：2021-10-14

申请号：US17357456

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Aaron Martin ,  Roger Cheng ,  Hari Venkatramani ,  Navneet Dour ,  Mozhgan Mansuri ,  Bryan Casper ,  Frank O'Mahony ,  Ganesh Balamurugan ,  Ajay Balankutty ,  Kuan Zhou ,  Sridhar Tirumalai ,  Krishnamurthy Venkataramana ,  Alex Thomas ,  Quoc Nguyen

IPC: H03K5/156 ,  H03L7/081 ,  G11C7/22 ,  G06F1/08 ,  G11C7/10

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

公开(公告)号：US20220200781A1

公开(公告)日：2022-06-23

申请号：US17341150

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Sandipan Kundu ,  Ajay Balankutty ,  Bong Chan Kim ,  Yutao Liu ,  Jihwan Kim ,  Kai Yu ,  Gurmukh Singh ,  Stephen Kim ,  Richard Packard ,  Frank O'Mahony

IPC: H04L7/033 ,  H03K5/135 ,  H04L7/00 ,  H03L7/087

Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.

公开(公告)号：US11070200B2

公开(公告)日：2021-07-20

申请号：US16144949

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Aaron Martin ,  Roger Cheng ,  Hari Venkatramani ,  Navneet Dour ,  Mozhgan Mansuri ,  Bryan Casper ,  Frank O'Mahony ,  Ganesh Balamurugan ,  Ajay Balankutty ,  Kuan Zhou ,  Sridhar Tirumalai ,  Krishnamurthy Venkataramana ,  Alex Thomas ,  Quoc Nguyen

IPC: H03K5/156 ,  H03L7/081 ,  G11C7/22 ,  G06F1/08 ,  G11C7/10

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

公开(公告)号：US20190115951A1

公开(公告)日：2019-04-18

申请号：US16206919

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Georgios Dogiamis ,  Jeff C. Morriss ,  Hyung-Jin Lee ,  Richard Dischler ,  Ajay Balankutty ,  Telesphor Kamgaing ,  Said Rami

IPC: H04B3/52 ,  H04L27/36

Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.

公开(公告)号：US12184751B2

公开(公告)日：2024-12-31

申请号：US17341150

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Sandipan Kundu ,  Ajay Balankutty ,  Bong Chan Kim ,  Yutao Liu ,  Jihwan Kim ,  Kai Yu ,  Gurmukh Singh ,  Stephen Kim ,  Richard Packard ,  Frank O'Mahony

IPC: H04L7/033 ,  H03K5/135 ,  H03L7/087 ,  H04L7/00

Abstract: A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.

公开(公告)号：US20220171718A1

公开(公告)日：2022-06-02

申请号：US17338479

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Sandipan Kundu ,  Jihwan Kim ,  Ajay Balankutty ,  Bong Chan Kim ,  Yutao Liu ,  Frank O'Mahony

IPC: G06F13/16 ,  H03K19/20 ,  H03K17/687 ,  G06F13/42 ,  G06F1/04

Abstract: A clock buffer that uses low-to-medium quality factor (e.g., QF of 2 to 5) inductors in shunt-series and in series-shunt configuration in high-speed clock distribution stages. Shunt-series and series-shunt inductors extend amplifier bandwidth. Applying shunt-series and series-shunt inductors to high-speed clock distribution filters jitter, attenuates supply noise, and improves fanout. An asymmetric multiplexer with inductors in shunt or in shunt-series configurations. Another asymmetric multiplexer with capacitively coupled tri-stateable inverter-based buffer stages. These two multiplexer techniques along with the ability to ‘hide’ a load of a non-preferred path at a virtual ground node of the shunt inductor, the multiplexer improves the jitter and power consumption of the preferred path significantly. A de-multiplexer (DeMux) is also shown using inductors. A combination of a shunt-multiplexer and an inductor-based DeMux is also discussed.

公开(公告)号：US09935063B2

公开(公告)日：2018-04-03

申请号：US15201375

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Yu Amos Zhang ,  Jihwan Kim ,  Ajay Balankutty ,  Anupriya Sriramulu ,  MD. Mohiuddin Mazumder ,  Frank O'Mahony ,  Zuoguo Wu ,  Kemal Aygun

IPC: H01L23/00 ,  H01L23/64 ,  H02H9/04 ,  H01L27/02 ,  H01L23/66

CPC classification number: H01L23/645 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0288 ,  H02H9/046

Abstract: Integrated circuit (IC) chip “on-die” inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.

公开(公告)号：US12111786B2

公开(公告)日：2024-10-08

申请号：US17338512

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Jihwan Kim ,  Ajay Balankutty ,  Sandipan Kundu ,  Stephen Kim ,  Frank O'Mahony ,  Kai Yu ,  Bong Chan Kim

IPC: G06F13/42 ,  G06F1/06 ,  G06F1/10 ,  H03K17/687 ,  H03L7/00

CPC classification number: G06F13/4291 ,  G06F1/06 ,  G06F1/10 ,  H03K17/6872 ,  H03K17/6874 ,  H03L7/00

Abstract: An apparatus enables a high-bandwidth 4-way data serializing (4:1 serializer) digital-to-analog converter. The apparatus uses active inductor-based bandwidth extension technique for two-stage driver enabling design of quarter-rate 4-way data serializing transmitter. The 4:1 serializer output bandwidth is extended by gate-resistor-peaked n-type transistor load working as an active inductor. A current steering switch with current source is used as the final driver. The 4:1 serializer includes a pulse width tuning technique with tunable ground voltage on the ground terminal of a pulse generator to tune an effective threshold voltage of the pulse generator. A Bessel-like LC filter is coupled to an output of the 4:1 serializer. The filter includes shunt peaking paths that provide zeros, which natively cancel large parasitic capacitance at a shunt peaking node. As such, active and passive devices including driver circuitry, ESD diodes, and any other sensing circuitry are flexibly added on any LC filter nodes.