公开(公告)号：US09030885B2

公开(公告)日：2015-05-12

申请号：US14549785

申请日：2014-11-21

Applicant: Intel Corporation

Inventor： Yogesh B Wakchaure ,  Kiran Pangal ,  Xin Guo ,  Qingru Meng ,  Hanmant P Belgal

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/26 ,  H01L27/115

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445 ,  G11C29/028 ,  H01L27/115

Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.

公开(公告)号：US20150078088A1

公开(公告)日：2015-03-19

申请号：US14549785

申请日：2014-11-21

Applicant: Intel Corporation

Inventor： Yogesh B Wakchaure ,  Kiran Pangal ,  Xin Guo ,  Qingru Meng ,  Hanmant P Belgal

IPC: G11C16/16

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445 ,  G11C29/028 ,  H01L27/115

Abstract: A flash memory device may include two or more flash memory cells organized as a NAND string in a block of flash memory cells, and flash cells, coupled to the NAND string at opposite ends, to function as select gates. The flash memory device may be capable of providing information related to a voltage threshold of the select gates to a flash controller, erasing the flash cells that function as select gates in response to a select gate erase command, and programming the flash cells that function as select gates in response to a select gate program command. A flash controller may be coupled to the flash memory device, and is capable of sending the select gate erase commend to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is above a predetermined voltage level, and sending the select gate program command to the flash memory device if the information provided by the flash memory device indicates that the voltage threshold of at least one of the select gates is outside of a predetermined voltage range.

Abstract translation: 闪存器件可以包括在快闪存储器单元块中被组织为NAND串的两个或更多个闪存单元，以及在相对端耦合到NAND串的闪存单元，用作选择门。 闪速存储器件可以能够向闪存控制器提供与选通门的电压阈值相关的信息，擦除响应于选择栅极擦除命令而用作选择栅极的闪存单元，以及编程用作 响应于选择门程序命令选择门。 闪存控制器可以耦合到闪存设备，并且如果闪存设备提供的信息指示至少一个选择门的电压阈值是 如果由闪速存储器件提供的信息指示至少一个选择门的电压阈值在预定电压范围之外，则将选择门程序命令发送到闪速存储器件。

公开(公告)号：US08832530B2

公开(公告)日：2014-09-09

申请号：US13627380

申请日：2012-09-26

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Prashant Damie

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/26

Abstract: Techniques associated with a read and write window budget for a two level memory (2LM) system may include establishing a read and write window budget for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may be part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory.

Abstract translation: 与两级存储器（2LM）系统的读和写窗口预算相关联的技术可以包括为包括第一级存储器和第二级存储器的2LM系统建立读和写窗口预算。 所建立的读写窗口预算可以包括第一组存储器地址和第二级存储器的第二组存储器地址的组合。 与第二组存储器地址相关联的非易失性存储器单元的单元阈值电压分布相比，第一组存储器地址可以与具有更宽的单元阈值电压分布的非易失性存储单元相关联。 根据一些示例，建立的读写窗口预算可以是满足给定量的存储器的完成时间阈值和对于给定的存储量的可接受的错误率阈值的满足读取或写入请求的策略的一部分 第二级内存。