公开(公告)号：US20240320001A1

公开(公告)日：2024-09-26

申请号：US18663228

申请日：2024-05-14

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Jesus CORBAL ,  Dan BAUM ,  Alexander HEINECKE ,  Elmoustapha OULD-AHMED-VALL

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Detailed herein are embodiment systems, processors, and methods for matrix move. For example, a processor comprising decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry to execute the decoded instruction to move each data element of the identified source matrix operand to corresponding data element position of the identified destination matrix operand is described.

公开(公告)号：US20240241722A1

公开(公告)日：2024-07-18

申请号：US18619570

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Naveen MELLEMPUDI ,  Alexander F. HEINECKE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Christopher J. HUGHES ,  Evangelos GEORGANAS ,  Zeev SPERBER ,  Amit GRADSTEIN ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F7/499 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F7/49915 ,  G06F9/30196 ,  G06F9/3887

Abstract: Systems, methods, and apparatuses relating to 8-bit floating-point matrix dot product instructions are described. A processor embodiment includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a destination matrix having single-precision elements, a first source matrix, and a second source matrix, the source matrices having elements that each comprise a quadruple of 8-bit floating-point values, the opcode to indicate execution circuitry is to cause, for each element of the first source matrix and corresponding element of the second source matrix, a conversion of the 8-bit floating-point values to single-precision values, a multiplication of different pairs of converted single-precision values to generate plurality of results, and an accumulation of the results with previous contents of a corresponding element of the destination matrix, decode circuitry to decode the fetched instruction, and the execution circuitry to respond to the decoded instruction as specified by the opcode.

公开(公告)号：US20240192954A1

公开(公告)日：2024-06-13

申请号：US18444254

申请日：2024-02-16

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Mark J. CHARNEY ,  Elmoustapha OULD-AHMED-VALL ,  Dan BAUM ,  Zeev SPERBER ,  Jesus CORBAL ,  Bret L. TOLL ,  Raanan SADE ,  Igor YANOVER ,  Yuri GEBIL ,  Rinat RAPPOPORT ,  Stanislav SHWARTSMAN ,  Menachem ADELMAN ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US20240134644A1

公开(公告)日：2024-04-25

申请号：US18400961

申请日：2023-12-29

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Dan BAUM ,  Zeev SPERBER ,  Jesus CORBAL ,  Elmoustapha OULD-AHMED-VALL ,  Bret L. TOLL ,  Mark J. CHARNEY ,  Barukh ZIV ,  Alexander HEINECKE ,  Milind GIRKAR ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

公开(公告)号：US20240126545A1

公开(公告)日：2024-04-18

申请号：US18397664

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Alexander F. HEINECKE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Raanan SADE ,  Menachem ADELMAN ,  Zeev SPERBER ,  Amit GRADSTEIN ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/3016 ,  G06F9/3802

Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.

公开(公告)号：US20240045690A1

公开(公告)日：2024-02-08

申请号：US18460497

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Dan BAUM ,  Michael ESPIG ,  James GUILFORD ,  Wajdi K. FEGHALI ,  Raanan SADE ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Bret TOLL ,  Elmoustapha OULD-AHMED-VALL ,  Mark J. CHARNEY ,  Vinodh GOPAL ,  Ronen ZOHAR ,  Alexander F. HEINECKE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30178 ,  G06F9/30145 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/3802

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US20230236834A1

公开(公告)日：2023-07-27

申请号：US18190761

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Alexander F. HEINECKE ,  Robert VALENTINE ,  Mark J. CHARNEY ,  Raanan SADE ,  Menachem ADELMAN ,  Zeev SPERBER ,  Amit GRADSTEIN ,  Simon RUBANOVICH

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/3016 ,  G06F9/3802

Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.

公开(公告)号：US20230236833A1

公开(公告)日：2023-07-27

申请号：US18100194

申请日：2023-01-23

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Menachem ADELMAN ,  Milind B. GIRKAR ,  Zeev SPERBER ,  Mark J. CHARNEY ,  Bret L. TOLL ,  Rinat RAPPOPORT ,  Jesus Corbal ,  Stanislav SHWARTSMAN ,  Dan BAUM ,  Igor YANOVER ,  Alexander F. HEINECKE ,  Barukh ZIV ,  Elmoustapha OULD-AHMED-VALL ,  Yuri GEBIL

IPC: G06F9/30 ,  G06F7/485 ,  G06F17/16 ,  G06F7/76 ,  G06F7/487 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F17/16 ,  G06F9/30112 ,  G06F7/762 ,  G06F9/3016 ,  G06F9/30196 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30185 ,  G06F7/4876 ,  G06F9/30145 ,  G06F9/30134 ,  G06F9/30149 ,  G06F9/3836 ,  G06F9/30032 ,  G06F9/3001 ,  G06F9/3818 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

公开(公告)号：US20230205522A1

公开(公告)日：2023-06-29

申请号：US17560557

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Robert VALENTINE ,  Wing Shek WONG ,  Jonathan COMBS ,  Mark CHARNEY

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30025 ,  G06F9/3818 ,  G06F9/30112

Abstract: Techniques for data type conversion via instruction are described. An exemplary instruction is to include fields for an opcode, an identification of a source operand, and an identification of destination operand, wherein the opcode is to indicate instruction processing circuitry is to convert odd 16-bit floating point values from the identified source operand into 32-bit floating point values and store the 32-bit floating point values in data element positions of the identified destination operand.

公开(公告)号：US20230102279A1

公开(公告)日：2023-03-30

申请号：US17485363

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Menachem ADELMAN ,  Robert VALENTINE ,  Dan BAUM ,  Amit GRADSTEIN ,  Simon RUBANOVICH ,  Regev SHEMY ,  Zeev SPERBER ,  Alexander HEINECKE ,  Christopher HUGHES ,  Evangelos GEORGANAS ,  Mark CHARNEY ,  Arik NARKIS ,  Rinat RAPPOPORT ,  Barukh ZIV ,  Yaroslav POLLAK ,  Nilesh JAIN ,  Yash AKHAURI ,  Brinda GANESH ,  Rajesh POORNACHANDRAN ,  Guy BOUDOUKH

IPC: G06F9/30 ,  G06F17/16

Abstract: Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.