公开(公告)号：US20190196826A1

公开(公告)日：2019-06-27

申请号：US15850071

申请日：2017-12-21

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Mark Charney ,  Jesus Corbal ,  Binwei Yang

IPC: G06F9/30 ,  G06F7/485

CPC classification number: G06F9/30145 ,  G06F7/485 ,  G06F9/30101

Abstract: An apparatus and method for performing addition of signed packed data values using rotation and halving. For example, one embodiment of a processor comprises: a decoder to decode an instruction to generate a decoded instruction, the instruction including an opcode, an immediate, and operands identifying a plurality of packed data source registers and a packed data destination register a first source register to store a first plurality of packed signed words; a second source register to store a second plurality of packed signed words; execution circuitry to execute the decoded instruction, the execution circuitry comprising: adder circuitry to add each packed signed word from the first source register with a selected packed signed word from the second source register to generate a plurality of signed word results, the adder circuitry to select each packed signed word from the second source register in accordance with a rotation value in the immediate of the instruction, the rotation value to indicate an amount of rotation to be applied to the packed signed words in the second source register prior to the adder circuitry performing the adding; and a destination register to store the plurality of signed word results in specified data element locations of the destination register.

公开(公告)号：US20190163473A1

公开(公告)日：2019-05-30

申请号：US15824333

申请日：2017-11-28

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Mark Charney ,  Raanan Sade ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Roman S. Dubtsov

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F7/4806 ,  G06F7/4812 ,  G06F9/3013 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3824 ,  G06F17/10

Abstract: An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

公开(公告)号：US20190102182A1

公开(公告)日：2019-04-04

申请号：US15721458

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Mark Charney ,  Robert Valentine ,  Binwei Yang

IPC: G06F9/30

Abstract: An apparatus and method for performing dual concurrent multiplications of packed data elements. For example one embodiment of a processor comprises: a decoder to decode a first instruction to generate a decoded instruction; a first source register to store a first plurality of packed data elements; a second source register to store a second plurality of packed data elements; execution circuitry to execute the decoded instruction, the execution circuitry comprising: multiplier circuitry to perform concurrent dual multiplications of a first packed data element from the first source register with a second packed data element from the second source register and a third packed data element from the first source register with a fourth packed data element from the second source register to generate first and second products, respectively, wherein the first and third packed data elements have a width twice as large as a width of the second and fourth packed data elements; the multiplier circuitry to select the first and third packed data elements from the first source register and the second and fourth packed data elements from the second source register in accordance with the immediate to generate the first and second products.

公开(公告)号：US10223114B1

公开(公告)日：2019-03-05

申请号：US15721602

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Venkateswara Madduri ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Mark Charney

IPC: G06F9/30 ,  G06F7/483

Abstract: Embodiments of instructions and methods of execution of said instructions and resources to execute said instructions are detailed. For example, in an embodiment, a processor comprising: decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a data element from a least significant packed data element position of the identified packed data source operand from a fixed-point representation to a floating point representation, store the floating point representation into a 32-bit least significant packed data element position of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand is described.

公开(公告)号：US20190042255A1

公开(公告)日：2019-02-07

申请号：US15858937

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to decode a store matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded store matrix pair instruction to store every element of left and right tiles of the identified source matrix to corresponding element positions of left and right tiles of the identified destination matrix, respectively, wherein the executing stores a chunk of C elements of one row of the identified source matrix at a time.

公开(公告)号：US20190042254A1

公开(公告)日：2019-02-07

申请号：US15858932

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to systems and methods to load a tile register pair. In one example, a processor includes: decode circuitry to decode a load matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded load matrix pair instruction to load every element of left and right tiles of the identified destination matrix from corresponding element positions of left and right tiles of the identified source matrix, respectively, wherein the executing operates on one row of the identified destination matrix at a time, starting with the first row.

公开(公告)号：US20190042235A1

公开(公告)日：2019-02-07

申请号：US15858916

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F9/30

Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (M,N) of the identified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the identified first source matrix by a corresponding nibble of a doubleword element (K,N) of the identified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element (M,N).

公开(公告)号：US10037208B2

公开(公告)日：2018-07-31

申请号：US15346531

申请日：2016-11-08

Applicant: Intel Corporation

Inventor： Mikhail Plotnikov ,  Andrey Naraikin ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Bret L. Toll ,  Jesus Corbal

IPC: G06F9/30 ,  G06F7/76

CPC classification number: G06F9/3013 ,  G06F7/764 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036

Abstract: A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.

公开(公告)号：US09996320B2

公开(公告)日：2018-06-12

申请号：US14757942

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Cristina S. Anderson ,  Marius A. Cornea-Hasegan ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine ,  Jesus Corbal ,  Nikita Astafev ,  Mark J. Charney ,  Milind B. Girkar ,  Amit Gradstein ,  Simon Rubanovich ,  Zeev Sperber

IPC: G06F7/48 ,  G06F7/487 ,  G06F7/485 ,  G06F7/499

CPC classification number: G06F7/4876 ,  G06F7/485 ,  G06F7/49915

Abstract: An example processor includes a register and a fused multiply-add (FMA) low functional unit. The register stores first, second, and third floating point (FP) values. The FMA low functional unit receives a request to perform an FMA low operation: multiplies the first FP value with the second FP value to obtain a first product value; adds the first product with the third FP value to generate a first result value; rounds the first result to generate a first FMA value; multiplies the first FP value with the second FP value to obtain a second product value; adds the second product value with the third FP value to generate a second result value; and subtracts the FMA value from the second result value to obtain a third result value, which can then be normalized and rounded (FMA low result) and sent the FMA low result to an application.

公开(公告)号：US08996923B2

公开(公告)日：2015-03-31

申请号：US13688544

申请日：2012-11-29

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Jesus Corbal ,  Mark J. Charney ,  Milind B. Girkar ,  Elmoustapha Ould-Ahmed-Vall ,  Robert Valentine

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/004 ,  G06F9/30036 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3865 ,  G06F11/0724 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0772

Abstract: A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.

Abstract translation: 处理器包括执行单元，耦合到执行单元的故障掩模以及耦合到执行单元的抑制掩模。 故障掩码是存储第一多个比特值以指示多元素向量的哪些元素具有响应于在执行单元中的元素上的指令的执行而产生的相关联的故障。 抑制掩模是存储第二多个位值，以指示哪个元件将被抑制相关联的故障。 所述处理器还包括计数器逻辑，以响应于与所述第一元件相关联并从所述故障掩模接收到的第一故障的指示来增加计数器，以及与所述第一元件相关联并从所述抑制掩码接收到的第一抑制的指示。 其他实施例被描述为所要求保护的。