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公开(公告)号:US20100181607A1
公开(公告)日:2010-07-22
申请号:US12749389
申请日:2010-03-29
申请人: Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
发明人: Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
IPC分类号: H01L27/06
CPC分类号: H01L28/91 , H01L27/10817 , H01L27/10852
摘要: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
摘要翻译: 描述了增加存储单元电容器的表面积的方法和装置。 形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。 衬底具有翅片。 第一绝缘层沉积在邻近鳍片的衬底上。 第二绝缘层上的开口形成在鳍上。 第一导电层沉积在第二绝缘层和鳍上。 第三绝缘层沉积在第一导电层上。 第二导电层沉积在第三绝缘层上。 第二导电层填充开口。 第二导电层是提供与上金属层的互连。 从第二绝缘层的顶表面去除第二导电层,第三绝缘层和第一导电层的部分。
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公开(公告)号:US07504808B2
公开(公告)日:2009-03-17
申请号:US11173065
申请日:2005-06-30
申请人: Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
发明人: Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Fabrice Paillet , Tanay Karnik , Vivek De
IPC分类号: G05F1/00
摘要: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
摘要翻译: 提供了一种包括多相变压器的多相DC-DC转换器,多相变压器包括多个输入电压端子和变压器输出电压端子,每个输入电压端子与相应的相位相关联。 将各相分配给多个输入电压端子的输入电压端子,以使多相变压器的输入电压端子处的纹波电流最小化。
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公开(公告)号:US20080237796A1
公开(公告)日:2008-10-02
申请号:US11731193
申请日:2007-03-30
申请人: Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
发明人: Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
CPC分类号: H01L28/91 , H01L27/10817 , H01L27/10852
摘要: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
摘要翻译: 描述了增加存储单元电容器的表面积的方法和装置。 形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。 衬底具有翅片。 第一绝缘层沉积在邻近鳍片的衬底上。 第二绝缘层上的开口形成在鳍上。 第一导电层沉积在第二绝缘层和鳍上。 第三绝缘层沉积在第一导电层上。 在第三绝缘层上沉积第二导电层。 第二导电层填充开口。 第二导电层是提供与上金属层的互连。 从第二绝缘层的顶表面去除第二导电层,第三绝缘层和第一导电层的部分。
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公开(公告)号:US07372382B2
公开(公告)日:2008-05-13
申请号:US11167978
申请日:2005-06-27
申请人: Peter Hazucha , Saravanan Rajapandian , Gerhard Schrom , Tanay Karnik , Vivek De
发明人: Peter Hazucha , Saravanan Rajapandian , Gerhard Schrom , Tanay Karnik , Vivek De
IPC分类号: H03M1/00
CPC分类号: G05F1/56
摘要: For one disclosed embodiment, error is sensed in a voltage at an output node. One or more analog signals are generated based on the sensed error. One or more generated analog signals are converted into one or more digital signals. The voltage at the output node is controlled in response to the one or more digital signals.
摘要翻译: 对于一个公开的实施例,在输出节点处的电压中感测到误差。 基于感测到的误差产生一个或多个模拟信号。 一个或多个产生的模拟信号被转换成一个或多个数字信号。 响应于一个或多个数字信号来控制输出节点处的电压。
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公开(公告)号:US20070076463A1
公开(公告)日:2007-04-05
申请号:US11239903
申请日:2005-09-30
申请人: Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
发明人: Ali Keshavarzi , Fabrice Paillet , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Mohsen Alavi , Vivek De
IPC分类号: G11C17/00
CPC分类号: G11C17/16 , G11C17/146 , G11C17/165 , G11C29/027
摘要: According to embodiments of the present invention, a one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. In on embodiment, access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.
摘要翻译: 根据本发明的实施例,一次可编程(OTP)单元包括耦合到反熔丝晶体管的存取晶体管。 在实施例中,存取晶体管具有大于反熔丝晶体管的栅极氧化物厚度的栅极氧化物厚度,使得如果对反熔丝晶体管进行编程,则跨越存取晶体管的栅极/漏极结的电压不足以导致 栅极氧化层的存取晶体管分解。 双栅氧化物OTP单元可以用于其中一次只编写一个OTP单元的阵列中。 双栅氧化物OTP电池也可用于其中同时编程几个OTP电池的阵列中。
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96.
公开(公告)号:US20070001762A1
公开(公告)日:2007-01-04
申请号:US11173760
申请日:2005-06-30
申请人: Gerhard Schrom , Peter Hazucha , Vivek De , Tanay Karnik
发明人: Gerhard Schrom , Peter Hazucha , Vivek De , Tanay Karnik
IPC分类号: H03F3/45
CPC分类号: H02M3/155 , G01R19/0092 , H02M2001/0009
摘要: A method is described comprising conducting a first current through a switching transistor. The method also comprises conducting a second current through a pair of transistors whose conductive channels are coupled in series with respect to each other and are together coupled in parallel across the switching transistor's conductive channel. The second current is less than and proportional to the first current.
摘要翻译: 描述了一种方法,其包括通过开关晶体管导通第一电流。 该方法还包括通过一对晶体管导通第二电流,导体沟道相对于彼此串联耦合并且一起并联耦合在开关晶体管的导电沟道上。 第二电流小于并与第一电流成比例。
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公开(公告)号:US20060291265A1
公开(公告)日:2006-12-28
申请号:US11169106
申请日:2005-06-27
申请人: Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Dinesh Somasekhar , Yibin Ye , Ali Keshavarzi , Muhammad Khellah , Vivek De
发明人: Gerhard Schrom , Fabrice Paillet , Tanay Karnik , Dinesh Somasekhar , Yibin Ye , Ali Keshavarzi , Muhammad Khellah , Vivek De
IPC分类号: G11C17/00
CPC分类号: G11C17/18
摘要: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
摘要翻译: 系统包括用于对存储器单元进行编程的上拉电路。 上拉电路可以包括电平移位器以接收控制信号,电源电压以及多个轨道电压中的一个或多个,多个轨道电压中的每一个基本上等于电源电压的相应整数倍, 并产生第二控制信号和共源共栅级。 共源共栅级可以包括多个晶体管,多个晶体管中的每一个的栅极电压至少部分地由第二控制信号,电源电压和多个轨道中的至少一个轨道 电压和输出节点以提供单元编程信号。
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公开(公告)号:US20060268626A1
公开(公告)日:2006-11-30
申请号:US11137905
申请日:2005-05-25
申请人: Fatih Hamzaoglu , Kevin Zhang , Nam Kim , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , Bo Zheng
发明人: Fatih Hamzaoglu , Kevin Zhang , Nam Kim , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , Bo Zheng
IPC分类号: G11C7/10
CPC分类号: G11C5/14 , G11C11/413
摘要: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
摘要翻译: 在一些实施例中,存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。 可以公开和/或要求保护其他实施例。
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99.
公开(公告)号:US07031203B2
公开(公告)日:2006-04-18
申请号:US11066395
申请日:2005-02-28
申请人: Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Vivek De
发明人: Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Vivek De
IPC分类号: G11C5/14
CPC分类号: H01L27/108 , G11C11/404 , G11C11/4085 , H01L29/7841
摘要: A DRAM memory cell uses a single transistor to perform the data storage and switching functions of a conventional cell. The transistor has a floating channel body which stores a potential that corresponds to one of two digital data values. The transistor further includes a gate connected to a first word line, a drain connected to a second word line, and a source connected to a bit line. By setting the word and bit lines to specific voltage states, the channel body stores a digital one potential as a result of impact ionization and a digital zero value as a result of forward bias of body-to-source junction.
摘要翻译: DRAM存储单元使用单个晶体管来执行常规单元的数据存储和切换功能。 晶体管具有浮置通道体,其存储对应于两个数字数据值之一的电位。 晶体管还包括连接到第一字线的栅极,连接到第二字线的漏极和连接到位线的源极。 通过将单词和位线设置为特定的电压状态,通道体由于碰撞电离而存储数字一个电位,并且由于体对源结的正向偏置而存储数字零值。
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公开(公告)号:US20060071646A1
公开(公告)日:2006-04-06
申请号:US10956285
申请日:2004-09-30
申请人: Fabrice Paillet , Ali Keshavarzi , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Alavi Mohsen , Vivek De
发明人: Fabrice Paillet , Ali Keshavarzi , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Stephen Tang , Alavi Mohsen , Vivek De
IPC分类号: H02J7/00
摘要: A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.
摘要翻译: 描述了一种在驱动电流通过电容器的同时在电容器的电介质材料内感应电介质击穿的方法。 电流特定于正在写入电容器的数据。 该方法还涉及通过解释由电容器电阻确定的电容器的行为来读取数据,其中电容器的电阻是诱导和驱动的结果。
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