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    INTELLIGENT ADJUSTMENT OF SCREEN REFRESH RATE
    92.
    发明申请
    INTELLIGENT ADJUSTMENT OF SCREEN REFRESH RATE 有权

    公开(公告)号：US20210201732A1

    公开(公告)日：2021-07-01

    申请号：US16917529

    申请日：2020-06-30

    Applicant: Micron Technology, Inc.

    Inventor： Ashish Ranjan ,  Carly M. Wantulok ,  Prateek Trivedi ,  Carla L. Christensen ,  Jun Huang ,  Avani F. Trived

    IPC: G09G3/20

    Abstract: Methods, systems, and devices that support a dynamic screen refresh rate are described. An electronic device may dynamically (e.g., autonomously, while operating) adjust the rate at which a screen is refreshed, such as to balance considerations such as user experience and power consumption by the electronic device. For example, the electronic device may use an increased refresh rate when executing applications for which user experience is enhanced by a higher refresh rate and may use a decreased refresh rate when executing other applications. As another example, the electronic device may use different refresh rates while executing different portions of the same application, as some aspects of an application (e.g., more intense portions of a video game) may benefit more than others from a higher refresh rate. The electronic device may also account of rother factors, such as battery level, when setting or adjusting the refresh rate of the screen.

    METHODS OF CONTEXT-BASED MOBILE DEVICE FEATURE CONTROL AND MOBILE DEVICES EMPLOYING THE SAME
    93.
    发明申请
    METHODS OF CONTEXT-BASED MOBILE DEVICE FEATURE CONTROL AND MOBILE DEVICES EMPLOYING THE SAME 有权

    公开(公告)号：US20210200885A1

    公开(公告)日：2021-07-01

    申请号：US16939499

    申请日：2020-07-27

    Applicant: Micron Technology, Inc.

    Inventor： Aparna U. Limaye ,  Lindsay Hamilton ,  Carla L. Christensen ,  Cipriana Forgy ,  Brandi M. Jones

    IPC: G06F21/62 ,  H04W12/00 ,  G06F21/32

    Abstract: Methods and systems for context-based mobile device feature control are provided. One method comprises determining, with a mobile device, one or more contexts corresponding to the mobile device; selecting, from a predetermined set of security protocols, a security protocol corresponding to the determined one or more contexts; and adjusting a permission setting for one or more functional features of the mobile device based upon the selected security protocol. One apparatus comprises one or more features configure to input data, output data, transform data, or a combination thereof; and a controller configured to: determine one or more contexts corresponding to the mobile computing device, to select, from a predetermined set of security protocols, a security protocol corresponding to the determined one or more contexts, and to adjust a permission setting for the one or more functional features based upon the selected security protocol.

    Managed NVM adaptive cache management
    94.
    发明授权
    Managed NVM adaptive cache management 有权

    公开(公告)号：US10572388B2

    公开(公告)日：2020-02-25

    申请号：US15691147

    申请日：2017-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Carla L. Christensen ,  Jianmin Huang ,  Sebastien Andre Jean ,  Kulachet Tanpairoj

    IPC: G06F12/08 ,  G06F12/02 ,  G06F3/06 ,  G06F12/0893

    Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.

    Non-volatile memory including selective error correction
    95.
    发明授权
    Non-volatile memory including selective error correction 有权

    公开(公告)号：US10169144B2

    公开(公告)日：2019-01-01

    申请号：US14997164

    申请日：2016-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Carla L. Christensen

    IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C29/04

    Abstract: Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. The control circuitry of the memory device is configured to retrieve the first information from the first memory area and store in the first information after the error correction engine performs an error detection operation on the first information. The control circuitry is configured to retrieve second information from the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.

    NON-VOLATILE MEMORY INCLUDING SELECTIVE ERROR CORRECTION
    96.
    发明申请
    NON-VOLATILE MEMORY INCLUDING SELECTIVE ERROR CORRECTION 审中-公开

    公开(公告)号：US20170206131A1

    公开(公告)日：2017-07-20

    申请号：US14997164

    申请日：2016-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Carla L. Christensen

    IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

    CPC classification number: G06F11/1072 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0688 ,  G11C2029/0411

    Abstract: Some embodiments include apparatuses and methods using a first memory area and a second memory area included a memory device, and using control circuitry included in the memory device to communicate with a memory controller. The memory controller includes an error correction engine. The control circuitry of the memory device is configured to retrieve the first information from the first memory area and store in the first information after the error correction engine performs an error detection operation on the first information. The control circuitry is configured to retrieve second information from the first memory area and store the second information in the second memory area without an additional error detection operation performed on the second information if a result from the error detection operation performed by the error correction engine on the first information meets a threshold condition.

    Display visibility block
    98.
    发明授权
    Display visibility block 有权

    公开(公告)号：US12147520B2

    公开(公告)日：2024-11-19

    申请号：US18213366

    申请日：2023-06-23

    Applicant: Micron Technology, Inc.

    Inventor： Bhumika Chhabra ,  Carla L. Christensen ,  Radhika Viswanathan ,  Zahra Hosseinimakarem

    IPC: G06F21/32 ,  G06F21/60 ,  G06V40/12 ,  G06V40/16 ,  G06V40/18 ,  G09G3/3208

    Abstract: Methods, apparatuses, and non-transitory machine-readable media for displaying information and/or images on a display of a computing device based on received data. Apparatuses can include a display screen, a memory resource, a recognition sensor, and a controller. An example controller can receive data and activate information and/or images on a display screen based in part on the received data. In another example, a method can include storing recognition data in a memory resource, receiving primary recognition data, comparing the primary recognition data to the stored recognition data, and activating the display screen for a viewing angle responsive to authentication of the primary recognition data through the comparison of the primary recognition data and the stored recognition data.

    RATING-BASED MAPPING OF DATA TO MEMORY
    99.
    发明申请
    RATING-BASED MAPPING OF DATA TO MEMORY 有权

    公开(公告)号：US20240370198A1

    公开(公告)日：2024-11-07

    申请号：US18666290

    申请日：2024-05-16

    Applicant: Micron Technology, Inc.

    Inventor： Carla L. Christensen ,  Gangotree Chakma ,  Yingqi Zheng ,  Yunfei Xu ,  Bhumika Chhabra

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for rating-based mapping of data to memory are described. A memory system may determine a first rating for a set of data selected for writing to a memory system. The memory system may select a target page of a block in the memory system for writing the set of data based at least in part on a second rating for the target page. The memory system may write the set of data to the target page based at least in part on the first rating for the set of data corresponding to the second rating for the target page.

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