公开(公告)号：US11599307B2

公开(公告)日：2023-03-07

申请号：US17331228

申请日：2021-05-26

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including maintaining a first group of tagged data from a host device at contiguous physical locations on a group of non-volatile memory cells of a storage system during system management operations on the group of non-volatile memory cells including the first group of tagged data while the first group of tagged data remains stored on the storage system and prioritizing, in the storage system, commands associated with the first group of tagged data.

公开(公告)号：US11587613B2

公开(公告)日：2023-02-21

申请号：US17572209

申请日：2022-01-10

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Ting Luo

IPC: G11C16/22 ,  G11C11/56 ,  G11C16/34 ,  G11C16/10

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

公开(公告)号：US20220404988A1

公开(公告)日：2022-12-22

申请号：US17895737

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F3/06 ,  G06F21/60 ,  G06F21/79

Abstract: Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

公开(公告)号：US11216193B2

公开(公告)日：2022-01-04

申请号：US16806720

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F21/00 ,  G06F3/06 ,  G06F12/02 ,  G06F21/79

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US20210406187A1

公开(公告)日：2021-12-30

申请号：US17471538

申请日：2021-09-10

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F12/0871 ,  G06F9/54 ,  G06F9/50 ,  G06F12/02

Abstract: Disclosed in some examples are methods, systems, and machine readable mediums that dynamically adjust the size of an L2P cache in a memory device in response to observed operational conditions. The L2P cache may borrow memory space from a donor memory location, such as a read or write buffer. For example, if the system notices a high amount of read requests, the system may increase the size of the L2P cache at the expense of the write buffer (which may be decreased). Likewise, if the system notices a high amount of write requests, the system may increase the size of the L2P cache at the expense of the read buffer (which may be decreased).

公开(公告)号：US11163692B2

公开(公告)日：2021-11-02

申请号：US16568962

申请日：2019-09-12

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F12/1009 ,  G06F12/02

Abstract: Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into multiple segments. Here, a bottom level of the translation table includes a logical to physical address pairing for a portion of a storage device and other levels of the translation table include references within the translation table. The multiple segments are written to the storage device. A first segment of the multiple segments is loaded to byte-addressable memory. A request for an address translation is received and determined to be for an address referred to by a second segment of the multiple segments. The first segment is then replaced with the second segment in the byte-addressable memory and the request is fulfilled using the second segment to locate a lower level of the translation table that includes the address translation.

公开(公告)号：US20210334016A1

公开(公告)日：2021-10-28

申请号：US16485374

申请日：2019-04-11

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F3/06 ,  G06F21/60 ,  G06F21/79

Abstract: Devices and techniques are disclosed herein for providing an improved Replay Protected Memory Block (RPMB) data frame and command queue for communication between a host device and a memory device.

公开(公告)号：US10936250B2

公开(公告)日：2021-03-02

申请号：US16580684

申请日：2019-09-24

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10 ,  G06F12/14 ,  G06F21/00

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.

公开(公告)号：US20200371709A1

公开(公告)日：2020-11-26

申请号：US16417029

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G06F13/16

Abstract: Apparatus and methods are disclosed, including enabling communication between a memory controller and multiple memory devices of a storage system using a storage-system interface, the multiple memory devices each comprising a device controller and a group of non-volatile memory cells, and compressing data using at least one of the device controllers prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system.

公开(公告)号：US10572388B2

公开(公告)日：2020-02-25

申请号：US15691147

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Carla L. Christensen ,  Jianmin Huang ,  Sebastien Andre Jean ,  Kulachet Tanpairoj

IPC: G06F12/08 ,  G06F12/02 ,  G06F3/06 ,  G06F12/0893

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The configuration (e.g., the size and position) of the SLC cache may have an impact on power consumption, speed, and other performance of the memory device. An operating system of an electronic device to which the memory device is installed may wish to achieve different performance of the device based upon certain conditions detectable by the operating system. In this way, the performance of the memory device can be customized by the operating system through adjustments of the performance characteristics of the SLC cache.