公开(公告)号：US06825709B2

公开(公告)日：2004-11-30

申请号：US10337193

申请日：2003-01-06

Applicant: Mario Motz

Inventor： Mario Motz

IPC: H01K3500

CPC classification number: G01R33/07 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A temperature compensation circuit for a Hall element has a first and a second band gap reference circuit. The Hall element is fed from an excitation current that is proportional to a first reference voltage produced in the first band gap reference circuit. Furthermore, a second band gap reference circuit has a second resistor of a different resistor type than the first resistor. A second reference voltage is dropped across the second resistor. Inputs of a comparator are connected to the Hall sensor and to the second resistor. The comparator compares the Hall voltage with the second reference voltage. The present temperature compensation circuit automatically compensates for manufacturing-dependent and temperature-dependent tolerances.

Abstract translation: 霍尔元件的温度补偿电路具有第一和第二带隙基准电路。 霍尔元件由与第一带隙基准电路中产生的第一参考电压成比例的激励电流馈送。 此外，第二带隙基准电路具有与第一电阻器不同的电阻器类型的第二电阻器。 第二个参考电压在第二个电阻上掉落。 比较器的输入端连接到霍尔传感器和第二个电阻器。 比较器比较霍尔电压和第二参考电压。 本温度补偿电路自动补偿制造依赖和温度相关的公差。

公开(公告)号：US06727693B2

公开(公告)日：2004-04-27

申请号：US10117829

申请日：2002-04-08

Applicant: Hans Altrichter ,  Mario Motz

Inventor： Hans Altrichter ,  Mario Motz

IPC: G01R3306

CPC classification number: H03K17/9517 ,  G01R33/07

Abstract: The circuit configuration converts an input signal into a binary output signal. The circuit has at least one comparator, at least one demodulation unit, and at least one clock unit. The demodulation unit has two or more capacitors and two or more switches controlled by the clock unit. The switches connect the capacitors of the demodulation unit to the comparator, and the comparator compares an input signal demodulated by the demodulation unit with a reference value and forms from that the binary output signal.

Abstract translation: 电路配置将输入信号转换为二进制输出信号。 电路具有至少一个比较器，至少一个解调单元和至少一个时钟单元。 解调单元具有两个或多个电容器和由时钟单元控制的两个或多个开关。 开关将解调单元的电容器连接到比较器，并且比较器将由解调单元解调的输入信号与参考值进行比较，并从二进制输出信号形成。

公开(公告)号：US06559721B2

公开(公告)日：2003-05-06

申请号：US10014001

申请日：2001-12-11

Applicant: Udo Ausserlechner ,  Mario Motz

Inventor： Udo Ausserlechner ,  Mario Motz

IPC: H03F318

CPC classification number: H03F3/72 ,  H03F1/523 ,  H03F3/3028 ,  H03F2203/7221

Abstract: A circuit configuration with an integrated amplifier is described. The amplifier has an output stage that is connected to a supply potential terminal and a reference potential terminal. A pair of complementary output transistors couples the amplifier with a tri-state output. Given an interruption of an operating-current supply that is connectible to the reference and supply potential terminals, the tri-state output is put into a high-impedance state by the circuit configuration. To this end, two blocking transistors are provided, which can be supplied by respective charge pump circuits. For instance, for sensor applications in which a high operational reliability is required, the present circuit configuration prevents the misinterpretation of measurement results given disturbances, for a small outlay.

公开(公告)号：US5530394A

公开(公告)日：1996-06-25

申请号：US318355

申请日：1994-10-05

Applicant: Lothar Blossfeld ,  Ulrich Theus ,  Mario Motz

Inventor： Lothar Blossfeld ,  Ulrich Theus ,  Mario Motz

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/0814 ,  H03K17/10 ,  H01J19/82 ,  G05F1/10 ,  G05F3/16 ,  H03K3/59

CPC classification number: H03K17/102 ,  H01L27/0266 ,  H01L27/092 ,  H03K17/08142 ,  H01L2924/0002

Abstract: In a CMOS circuit having at least a first subcircuit coupled between a first point of potential and a first circuit node, and having a second subcircuit coupled between a second circuit node and a second point of potential, said first and second circuit nodes being coupled together, the improvement in combination therewith, comprising: first circuit means coupled to the first point of potential for converting the first potential to a third potential as a function of the magnitude of said first potential, said third potential being of a value inbetween the first and second potentials; a FET having source, drain, gate and well terminals, said source terminal being coupled to said well terminal and to said first circuit node, said third potential being applied to said gate terminal, said drain terminal being coupled to said second circuit node; wherein said FET, in conjunction with said first circuit means, operates to selectively provide a difference in potential between said first and second circuit nodes, thereby preventing voltage breakdown within said subcircuits.

Abstract translation: 在具有耦合在第一电位点和第一电路节点之间的至少第一子电路并且具有耦合在第二电路节点和第二电位点之间的第二子电路的CMOS电路中，所述第一和第二电路节点耦合在一起 与其组合的改进包括：耦合到第一电位点的第一电路装置，用于将第一电位转换为第三电位，作为所述第一电位的大小的函数，所述第三电位在第一和第 第二个潜力; 具有源极，漏极，栅极和阱端子的FET，所述源极端子耦合到所述阱极端子和所述第一电路节点，所述第三电位被施加到所述栅极端子，所述漏极端子耦合到所述第二电路节点; 其中所述FET结合所述第一电路装置操作以选择性地提供所述第一和第二电路节点之间的电位差，由此防止所述子电路内的电压击穿。

公开(公告)号：US09222992B2

公开(公告)日：2015-12-29

申请号：US12630596

申请日：2009-12-03

Applicant: Udo Ausserlechner ,  Mario Motz

Inventor： Udo Ausserlechner ,  Mario Motz

IPC: G01R15/20 ,  G01R33/07

CPC classification number: G01R15/202 ,  G01R15/207 ,  G01R19/0092 ,  G01R33/072 ,  G01R33/075

Abstract: Embodiments related to magnetic current sensors, systems and methods. In an embodiment, a magnetic current sensor integrated in an integrated circuit (IC) and housed in an IC package comprises an IC die formed to present at least three magnetic sense elements on a first surface, a conductor, and at least one slot formed in the conductor, wherein a first end of the at least one slot and at least one of the magnetic sense elements are relatively positioned such that the at least one of the magnetic sense elements is configured to sense an increased magnetic field induced in the conductor proximate the first end of the at least one slot.

Abstract translation: 与磁流传感器，系统和方法相关的实施例。 在一个实施例中，集成在集成电路（IC）中并且容纳在IC封装中的磁流传感器包括IC模具，其形成为在第一表面，导体和至少一个槽上形成至少三个磁感应元件 所述导体，其中所述至少一个狭槽的第一端和所述磁感应元件中的至少一个相对定位成使得所述至少一个所述磁感应元件被配置为感测在所述导体中感应的增加的磁场， 至少一个槽的第一端。

公开(公告)号：US09094015B2

公开(公告)日：2015-07-28

申请号：US13006654

申请日：2011-01-14

Applicant: Mario Motz

Inventor： Mario Motz

IPC: G01B7/30 ,  H03K17/94 ,  G01P3/489 ,  G01P13/00 ,  G01R33/00

CPC classification number: H03K17/9517 ,  G01D5/142 ,  G01P3/489 ,  G01P13/00 ,  G01R17/02 ,  G01R19/0092 ,  G01R33/0029 ,  H03K5/2472 ,  H03K17/94

Abstract: One embodiment of the present invention relates to a method and apparatus to perform a low power activation of a system by measuring the slope of a digital signal corresponding to a motion sensor measurement value. In one embodiment, a low power activation circuit is coupled to magnetic motion sensor configured to output a magnetic signal proportional to a measured magnetic field. The low power activation circuit may comprise a digital tracking circuit configured to provide a digital signal that tracks the magnetic field and a difference detector configured to detect a difference between a current digital signal and a prior digital signal stored in a digital storage means. If the detected difference is larger than a digital reference level, an activation signal is output to awaken a system from a sleep mode.

Abstract translation: 本发明的一个实施例涉及通过测量对应于运动传感器测量值的数字信号的斜率来执行系统的低功率激活的方法和装置。 在一个实施例中，低功率激活电路耦合到磁性运动传感器，该磁性运动传感器被配置为输出与测量的磁场成比例的磁信号。 低功率激活电路可以包括被配置为提供跟踪磁场的数字信号的数字跟踪电路和被配置为检测当前数字信号和存储在数字存储装置中的先前数字信号之间的差异的差分检测器。 如果检测到的差异大于数字参考电平，则输出激活信号以从睡眠模式唤醒系统。

公开(公告)号：US20140077873A1

公开(公告)日：2014-03-20

申请号：US13617547

申请日：2012-09-14

Applicant: Mario Motz ,  Manfred Bresch

Inventor： Mario Motz ,  Manfred Bresch

IPC: H03F1/02

CPC classification number: H03F3/38 ,  H03F1/02 ,  H03F3/387 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2200/333 ,  H03F2200/411

Abstract: The present disclosure relate to a sensor system having a low offset error. In some embodiments, the sensor system comprises a sensor configured to generate a sensor signal, which is provided to a main signal path having a first chopping correction circuit and a second chopping correction circuit. The first and second chopping correction circuit chop the sensor signal at first and second frequencies to reduce offset errors, but in doing so generate first and second chopping ripple errors. A first digital offset feedback loop generates a first compensation signal, which is fed back into the main signal path to mitigate the first chopping ripple error. A second digital offset feedback loop generates a second compensation signal, which is fed back into the main signal path to mitigate the second chopping ripple error.

公开(公告)号：US20140043085A1

公开(公告)日：2014-02-13

申请号：US13570969

申请日：2012-08-09

Applicant: Mario Motz

Inventor： Mario Motz

IPC: G05F1/10

CPC classification number: G01R33/07 ,  G01R33/0035 ,  G01R33/0041

Abstract: A feedback control circuit comprises an adjustable element, a main signal path and a feedback control loop. The adjustable element is configured to offset a signal in accordance with an offset control signal and output an offset signal. The main signal path comprises a first comparator to process the offset signal to output a main signal. The feedback control loop comprises a second comparator to process the offset signal to output a tracking signal, a first signal evaluator to evaluate the tracking signal and a first controller to output the offset control signal based on the evaluated tracking signal. The feedback control loop further comprises a second signal evaluator to detect a difference between a signal property of the main signal and the tracking signal and a second controller to control one of the comparators or the adjustable element such that the difference is reduced.

Abstract translation: 反馈控制电路包括可调元件，主信号路径和反馈控制回路。 可调节元件被配置为根据偏移控制信号偏移信号并输出​​偏移信号。 主信号路径包括用于处理偏移信号以输出主信号的第一比较器。 反馈控制回路包括第二比较器，用于处理偏移信号以输出跟踪信号;第一信号评估器，用于评估跟踪信号;以及第一控制器，基于所估计的跟踪信号输出偏移控制信号。 反馈控制环路还包括第二信号评估器，用于检测主信号的信号特性和跟踪信号之间的差异;以及第二控制器，用于控制比较器之一或可调节元件，使得差值减小。

公开(公告)号：US20140003464A1

公开(公告)日：2014-01-02

申请号：US13540081

申请日：2012-07-02

Applicant: Udo Ausserlechner ,  Mario Motz

Inventor： Udo Ausserlechner ,  Mario Motz

IPC: G01B7/16 ,  G01K7/00 ,  G01B5/30

CPC classification number: G01D3/021

Abstract: Embodiments relate to stress compensation in differential sensors. In an embodiment, instead of compensating for stress on each sensor element independently, stress compensation circuitry aims to remove stress-related mismatch between two sensor elements using the sensor elements themselves to detect the mismatch. A circuit can be implemented in embodiments to detect mechanical stress-related mismatch between sensor elements using the sensor elements, and tune the output signal by a compensation factor to eliminate the mismatch. Embodiments are therefore less complicated and less expensive than conventional approaches. While embodiments have applicability to virtually any differential sensor, including magnetic field, pressure, temperature, current and speed, an example embodiment discussed herein relates to magnetic field.

Abstract translation: 实施例涉及差动传感器中的应力补偿。 在一个实施例中，代替独立地补偿每个传感器元件上的应力，应力补偿电路旨在消除使用传感器元件本身的两个传感器元件之间的应力相关失配，以检测失配。 在实施例中可以实现电路以使用传感器元件检测传感器元件之间的机械应力相关失配，并且通过补偿因子来调整输出信号以消除不匹配。 因此，实施例比常规方法更不复杂和便宜。 虽然实施例可适用于几乎任何包括磁场，压力，温度，电流和速度的差分传感器，但本文讨论的示例实施例涉及磁场。

公开(公告)号：US20130214775A1

公开(公告)日：2013-08-22

申请号：US13400214

申请日：2012-02-20

Applicant: Udo Ausserlechner ,  Mario Motz

Inventor： Udo Ausserlechner ,  Mario Motz

IPC: G01R33/06

CPC classification number: H01L43/065 ,  G01R33/077

Abstract: A vertical Hall device indicative of a magnetic field parallel to a surface of a substrate comprises first, second, third and fourth terminals. The vertical Hall device further comprises contacts to generate a Hall effect signal indicative of the magnetic field. At least one pair of Hall effect regions is provided which comprises a first Hall effect region and a second Hall effect region formed in the substrate. A first group of the contacts is arranged in or at a surface of the first Hall effect region, the first group comprising a first and second outmost contacts. A second group of contacts is arranged in or at a surface of the second Hall effect region, the second group comprising third and fourth outmost contacts. Each of the first, second, third and fourth terminals is connected to a same number of outmost contacts.

Abstract translation: 指示平行于衬底的表面的磁场的垂直霍尔器件包括第一，第二，第三和第四端子。 垂直霍尔装置还包括产生表示磁场的霍尔效应信号的触点。 提供至少一对霍尔效应区域，其包括在基板中形成的第一霍尔效应区域和第二霍尔效应区域。 第一组触点布置在第一霍尔效应区域的表面或其表面上，第一组包括第一和第二最外面的触点。 第二组触点布置在第二霍尔效应区域的表面中或表面上，第二组包括第三和第四最外面的触点。 第一，第二，第三和第四端子中的每一个连接到相同数量的最外面的触点。