公开(公告)号：US20220036960A1

公开(公告)日：2022-02-03

申请号：US17365003

申请日：2021-07-01

Applicant: Micron Technology, Inc.

Inventor： Mark D. Ingram ,  Todd Jackson Plum ,  Scott E. Schaefer ,  Aaron P. Boehm ,  Scott D. Van De Graaff

IPC: G11C29/44 ,  G11C29/12 ,  G06F12/02

Abstract: Methods, systems, and devices for monitoring and adjusting access operations at a memory device are described to support integrating monitors or sensors for detecting memory device health issues, such as those resulting from device access or wear. The monitoring may include traffic monitoring of access operations performed at various components of the memory device, or may include sensors that may measure parameters of components of the memory device to detect wear. The traffic monitoring or the parameters measured by the sensors may be represented by a metric related to access operations for the memory device. The memory device may use the metric (e.g., along with a threshold) to determine whether to adjust a parameter associated with performing access operations received by the memory device, in order to implement a corrective action.

公开(公告)号：US11182244B2

公开(公告)日：2021-11-23

申请号：US16578094

申请日：2019-09-20

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/409 ,  G06F12/14

Abstract: Methods, systems, and devices for error correction management are described. A system may include a memory device that supports internal detection and correction of corrupted data, and whether such detection and correction functionality is operating properly may be evaluated. A known error may be included (e.g., intentionally introduced) into either data stored at the memory device or an associated error correction codeword, among other options, and data or other indications subsequently generated by the memory device may be evaluated for correctness in view of the error. Thus, either the memory device or a host device coupled with the memory device, among other devices, may determine whether error detection and correction functionality internal to the memory device is operating properly.

公开(公告)号：US20210311642A1

公开(公告)日：2021-10-07

申请号：US17354658

申请日：2021-06-22

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06

Abstract: Methods, systems, and devices for row hammer protection for a memory device are described. A memory device may identify a threshold of related row accesses (e.g., access commands or activates to a same row address or a row address space) for a memory array. In a first operation mode, the memory device may execute commands received from a host device on the memory array. The memory device may determine that a metric of the received row access commands satisfies the threshold of related row accesses. The memory device may switch the memory array from the first operation mode to a second operation mode based on satisfying the threshold. The second operation mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.

公开(公告)号：US11100998B2

公开(公告)日：2021-08-24

申请号：US17019602

申请日：2020-09-14

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Aaron P. Boehm ,  Fa-Long Luo

IPC: G11C7/00 ,  G11C16/10 ,  G11C7/10 ,  G11C16/08 ,  G06F17/16 ,  G11C8/14 ,  G11C5/02 ,  G11C16/04

Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

公开(公告)号：US20210248033A1

公开(公告)日：2021-08-12

申请号：US17152036

申请日：2021-01-19

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30

Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.

公开(公告)号：US11054995B2

公开(公告)日：2021-07-06

申请号：US16546252

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Aaron P. Boehm

IPC: G06F3/06

Abstract: Methods, systems, and devices for row hammer protection for a memory device are described. A memory device may identify a threshold of related row accesses (e.g., access commands or activates to a same row address or a row address space) for a memory array. In a first operation mode, the memory device may execute commands received from a host device on the memory array. The memory device may determine that a metric of the received row access commands satisfies the threshold of related row accesses. The memory device may switch the memory array from the first operation mode to a second operation mode based on satisfying the threshold. The second operation mode may restrict access to at least one row of the memory, while the first mode may be less restrictive. Additionally or alternatively, the memory device may notify the host device that the metric has satisfied the threshold.

公开(公告)号：US20210191660A1

公开(公告)日：2021-06-24

申请号：US17098096

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F3/06

Abstract: Methods, systems, and devices for address verification for a memory device are described. When a memory device receives a write command, the memory device may store, in association with the data written, an indication of a write address associated with the write command. When the memory device receives a read command, the memory device may retrieve data and a previously stored write address associated with the retrieved data, and the memory device may verify a read address associated with the read command against the previously stored write address associated with retrieved data. Thus, for example, the memory device may verify whether data read from the memory array based on an address associated with a read command is data that, when previously written to the memory array, was written in response to a write command associated with a matching address.

公开(公告)号：US20200341847A1

公开(公告)日：2020-10-29

申请号：US16839438

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Aaron P. Boehm ,  Scott E. Schaefer

IPC: G06F11/14 ,  G06F13/16

Abstract: Methods, systems, and devices for performing safety event detection for a memory device are described. For example, a memory array of a memory device may operate in a first mode of operation (e.g., a normal mode of operation). An event associated with a reduction of data integrity for the memory array may be detected. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. Based on the detected event, it may be determined whether to adjust the operation of the memory device to a second mode of operation (e.g., a safe mode of operation). The second mode of operation may correspond to a mode of operation that increases data retention characteristics.

公开(公告)号：US20200278908A1

公开(公告)日：2020-09-03

申请号：US16803856

申请日：2020-02-27

Applicant: Micron Technology, Inc.

Inventor： Scott E. Schaefer ,  Jongtae Kwak ,  Aaron P. Boehm

IPC: G06F11/10 ,  G11C7/10

Abstract: Methods, systems, and devices for extended error detection for a memory device are described. For example, during a read operation, the memory device may perform an error detection operation capable of detecting single-bit errors, double-bit errors, and errors that impact more than two bits and indicate the detected error to a host device. The memory device may use parity information to perform an error detection procedure to detect and/or correct errors within data retrieved during the read operation. In some cases, the memory device may associate each bit of the data read during the read operation with two or more bits of parity information. For example, the memory device may use two or more sets of parity bits to detect errors within a matrix of the data. Each set of parity bits may correspond to a dimension of the matrix of data.

公开(公告)号：US20200100270A1

公开(公告)日：2020-03-26

申请号：US16142025

申请日：2018-09-26

Applicant: Micron Technology, Inc.

Inventor： Fa-Long Luo ,  Glen E. Hush ,  Aaron P. Boehm

IPC: H04W72/12 ,  H04B1/38 ,  G06F9/30

Abstract: Systems, apparatuses and method related to remotely executable instructions are described. A device may be wirelessly coupled to (e.g., physically separated) another device, which may be in a physically separate device. The another device may remotely execute instructions associated with performing various operations, which would have been entirely executed at the device absent the another device. The outputs obtained as a result of the execution may be transmitted, via the transceiver, back to the device via a wireless communication link (e.g., using resources of an ultra high frequency (UHF), super high frequency (SHF), extremely high frequency (EHF), and/or tremendously high frequency (THF) bands). The another device at which the instructions are remotely executable may include memory resources, processing resources, and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g., device-to-device) or indirectly (e.g., via a base station).