公开(公告)号：US20240120320A1

公开(公告)日：2024-04-11

申请号：US18389752

申请日：2023-12-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/473 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/473 ,  H01L23/481 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08146 ,  H01L2225/06544 ,  H01L2924/1421 ,  H01L2924/1431

Abstract: A 3D device, the device including: at least one first level including logic circuits; at least one second level bonded to the first level, where the at least one second level includes a plurality of transistors; connectivity structures, where the connectivity structures include a plurality of transmission lines, where the plurality of transmission lines are designed to conduct radio frequencies (“RF”) signals, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions; and a plurality of vias disposed through the at least one second level, where at least a majority of the plurality of vias have a diameter of less than 5 micrometers.

公开(公告)号：US11930648B1

公开(公告)日：2024-03-12

申请号：US18388840

申请日：2023-11-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/14511

Abstract: A semiconductor device including: a first level including first memory arrays, a plurality of first transistors, and a plurality of first metal layers; a second level disposed on top of the first level, where the second level includes second memory arrays; a third level disposed on top of the second level, where the third level includes a plurality of third transistors and a plurality of third metal layers, where the third level is bonded to the second level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes, where the second filled holes are aligned to the first filled holes with a more than 1 nm but less than 40 nm alignment error, and where the third level includes decoder circuits.

公开(公告)号：US11910622B1

公开(公告)日：2024-02-20

申请号：US18384304

申请日：2023-10-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H10B80/00 ,  H10B43/27 ,  H10B43/30 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B43/27 ,  H10B43/30 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A 3D memory device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of memory-line pillars, where each memory-line pillar of the plurality of memory-line pillars is directly connected to a plurality of the source or the drain, where the plurality of memory-line pillars are vertically oriented, where the channel is horizontally-oriented and a plurality are connected to a body pillar, where the body pillar is at least temporary connected to a negative bias, the at least one memory transistor is self-aligned to an overlaying another memory transistor, both being processed following a same lithography step; a control level including a memory controller circuit and is hybrid bonded to the first structure.

公开(公告)号：US20230187397A1

公开(公告)日：2023-06-15

申请号：US18106484

申请日：2023-02-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L23/00 ,  H01L25/16 ,  H01L23/473 ,  H01L23/66 ,  H10B80/00

CPC classification number: H01L24/08 ,  H01L23/66 ,  H01L23/473 ,  H01L24/80 ,  H01L25/16 ,  H01L25/167 ,  H10B80/00 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/8013 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1011 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1443 ,  H01L2924/10253

Abstract: A 3D semiconductor device comprising: a first level; and a second level, wherein said first level comprises single crystal silicon and a plurality of logic circuits, wherein said plurality of logic circuits each comprise first transistors, wherein said second level is disposed above said first level and comprises a plurality of arrays of memory cells, said second level comprises a plurality of second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said first level is bonded to said second level, wherein said bonded comprises regions of oxide to oxide bonds, wherein said bonded comprises regions of metal to metal bonds; and a thermal isolation layer disposed between said first level and said second level, wherein said thermal isolation layer provides a greater than 20° C. differential temperature between said first level and said second level during nominal operation of said device.

公开(公告)号：US11600586B2

公开(公告)日：2023-03-07

申请号：US17951099

申请日：2022-09-23

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/48 ,  H01L25/00

Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least eight electronic circuit units (ECUs), where each of the at least eight ECUs includes a first circuit, the first circuit including a portion of the first transistors, where each of the at least eight ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the at least eight ECUs includes a first vertical bus, where the first vertical bus includes greater than eight pillars and less than three hundred pillars, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.

公开(公告)号：US20230018701A1

公开(公告)日：2023-01-19

申请号：US17948225

申请日：2022-09-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: G11C7/18 ,  G11C7/12 ,  G11C16/04 ,  G11C16/24 ,  H01L27/11578

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the device includes a temperature sensor.

公开(公告)号：US11488939B2

公开(公告)日：2022-11-01

申请号：US17581977

申请日：2022-01-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A 3D device comprising: a first level comprising first transistors, said first level comprising a first interconnect; a second level comprising second transistors, said second level overlaying said first level; a third level comprising third transistors, said third level overlaying said second level; a plurality of electronic circuit units (ECUs), wherein each of said plurality of ECUs comprises a first circuit, said first circuit comprising a portion of said first transistors, wherein each of said plurality of ECUs comprises a second circuit, said second circuit comprising a portion of said second transistors, wherein each of said plurality of ECUs comprises a third circuit, said third circuit comprising a portion of said third transistors, wherein each of said ECUs comprises a vertical bus, wherein said vertical bus comprises greater than eight pillars and less than three hundred pillars and provides electrical connections between said first circuit and said second circuit.

公开(公告)号：US20220231052A1

公开(公告)日：2022-07-21

申请号：US17712875

申请日：2022-04-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L27/11597 ,  H01L25/065 ,  H01L27/11587 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/14 ,  G11C11/22 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.

公开(公告)号：US20220130847A1

公开(公告)日：2022-04-28

申请号：US17567049

申请日：2021-12-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582

Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.

公开(公告)号：US11296106B2

公开(公告)日：2022-04-05

申请号：US17484394

申请日：2021-09-24

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

IPC: H01L27/11578 ,  H01L27/11573

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented; and a level of memory control circuits, where the memory control circuits is disposed either above or below the plurality of memory cells.