公开(公告)号：US20160057081A1

公开(公告)日：2016-02-25

申请号：US14464700

申请日：2014-08-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Ronald N. Fortino

IPC: H04L12/935 ,  H04L12/863 ,  H04L12/947

CPC classification number: H04L49/3018 ,  H04L47/624 ,  H04L49/252

Abstract: Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI addressing mode in communicating with the packet engine and in instructing the packet engine to store packet portions. A PDRSD requests a PPI from the packet engine, and is allocated a PPI by the packet engine, and then tags the packet portion to be written with the PPI and sends the packet portion and the PPI to the packet engine. Once the packet portion has been processed, a PPI de-allocation command causes the packet engine to de-allocate the PPI so that the PPI is available for allocating in association with another packet portion.

Abstract translation: 在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。 不是将PDRSD管理分组部分存储到存储器中，而是提供分组引擎。 PDRSD使用PPI寻址模式与分组引擎进行通信，并指示分组引擎存储分组部分。 PDRSD从分组引擎请求PPI，并由分组引擎分配PPI，然后用PPI标记要写入的分组部分，并将分组部分和PPI发送到分组引擎。 一旦分组部分被处理，PPI解除分配命令使分组引擎去分配PPI，使得PPI可用于与另一分组部分相关联地分配。

公开(公告)号：US20160034257A1

公开(公告)日：2016-02-04

申请号：US14448980

申请日：2014-07-31

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F7/72

CPC classification number: H04L9/3239 ,  G09C1/00 ,  H04L9/0643 ,  H04L2209/12

Abstract: A processor includes a hash register and a hash generating circuit. The hash generating circuit includes a novel programmable nonlinearizing function circuit as well as a modulo-2 multiplier, a first modulo-2 summer, a modulor-2 divider, and a second modulo-2 summer. The nonlinearizing function circuit receives a hash value from the hash register and performs a programmable nonlinearizing function, thereby generating a modified version of the hash value. In one example, the nonlinearizing function circuit includes a plurality of separately enableable S-box circuits. The multiplier multiplies the input data by a programmable multiplier value, thereby generating a product value. The first summer sums a first portion of the product value with the modified hash value. The divider divides the resulting sum by a fixed divisor value, thereby generating a remainder value. The second summer sums the remainder value and the second portion of the input data, thereby generating a hash result.

Abstract translation: 处理器包括散列寄存器和散列产生电路。 哈希发生电路包括一个新颖的可编程非线性函数电路以及模2乘法器，第一模2夏，模2分频器和第二模2夏。 非线性化函数电路从散列寄存器接收散列值，并执行可编程非线性函数，从而生成散列值的修改版本。 在一个示例中，非线性化功能电路包括多个可单独使能的S盒电路。 乘法器将输入数据乘以可编程乘数值，从而生成乘积值。 第一个夏季用修改的哈希值来计算产品值的第一部分。 分频器将结果总和除以固定除数值，从而生成余数值。 第二个夏天将剩余值和输入数据的第二部分相加，从而生成散列结果。

公开(公告)号：US20150370561A1

公开(公告)日：2015-12-24

申请号：US14311222

申请日：2014-06-20

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30069 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/3802

Abstract: A pipelined run-to-completion processor executes a conditional skip instruction. If a predicate condition as specified by a predicate code field of the skip instruction is true, then the skip instruction causes execution of a number of instructions following the skip instruction to be “skipped”. The number of instructions to be skipped is specified by a skip count field of the skip instruction. In some examples, the skip instruction includes a “flag don't touch” bit. If this bit is set, then neither the skip instruction nor any of the skipped instructions can change the values of the flags. Both the skip instruction and following instructions to be skipped are decoded one by one in sequence and pass through the processor pipeline, but the execution stage is prevented from carrying out the instruction operation of a following instruction if the predicate condition of the skip instruction was true.

Abstract translation: 流水线运行到完成处理器执行条件跳转指令。 如果由跳过指令的谓词代码字段指定的谓词条件为真，则跳过指令导致跳过指令之后的多个指令的执行被“跳过”。 要跳过的指令的数量由跳过指令的跳过计数字段指定。 在一些示例中，跳过指令包括“标志不触摸”位。 如果该位置位，则跳过指令和任何跳过的指令都不能更改标志的值。 跳过指令和要跳过的以下指令均按顺序逐个解码，并通过处理器流水线，但如果跳过指令的谓词条件为真，则禁止执行阶段执行后续指令的指令操作 。

公开(公告)号：US20150317163A1

公开(公告)日：2015-11-05

申请号：US14267342

申请日：2014-05-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/30079 ,  G06F9/30134 ,  G06F9/30149 ,  G06F9/32 ,  G06F9/355 ,  G06F9/3802 ,  G06F9/3869

Abstract: A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.

Abstract translation: 流水线运行完成处理器不包括指令计数器，并且仅获取指令：由于通过输入数据值和/或初始提取信息值从外部提示，或作为执行执行的结果 指令。 最初处理器没有计时。 输入值启动，启动处理器开始计时，并从表中的代码段获取指令块。 输入数据值和/或初始获取信息值确定从其获取块的部分和表。 LUT将初始获取信息值中的表号转换为找到表的基地址。 在代码段的末尾获取指令导致程序执行从一个部分跳转到另一个部分。 完成的指令将输出一个输出数据值，并停止处理器的时钟。

公开(公告)号：US20150317160A1

公开(公告)日：2015-11-05

申请号：US14267298

申请日：2014-05-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/32 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/3867 ,  G06F9/3879

Abstract: A pipelined run-to-completion processor includes no instruction counter and only fetches instructions either: as a result of being prompted from the outside by an input data value and/or an initial fetch information value, or as a result of execution of a fetch instruction. Initially the processor is not clocking. An incoming value kick-starts the processor to start clocking and to fetch a block of instructions from a section of code in a table. The input data value and/or the initial fetch information value determines the section and table from which the block is fetched. A LUT converts a table number in the initial fetch information value into a base address where the table is found. Fetch instructions at the ends of sections of code cause program execution to jump from section to section. A finished instruction causes an output data value to be output and stops clocking of the processor.

Abstract translation: 流水线运行完成处理器不包括指令计数器，并且仅获取指令：由于通过输入数据值和/或初始提取信息值从外部提示，或作为执行执行的结果 指令。 最初处理器没有计时。 输入值启动，启动处理器开始计时，并从表中的代码段获取指令块。 输入数据值和/或初始获取信息值确定从其获取块的部分和表。 LUT将初始获取信息值中的表号转换为找到表的基地址。 在代码段的末尾获取指令导致程序执行从一个部分跳转到另一个部分。 完成的指令将输出一个输出数据值，并停止处理器的时钟。

公开(公告)号：US20150220449A1

公开(公告)日：2015-08-06

申请号：US14172844

申请日：2014-02-04

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Rolf Neugebauer

IPC: G06F12/10 ,  G06F13/42

CPC classification number: G06F13/4234 ,  G06F9/45558 ,  G06F12/10 ,  G06F21/53 ,  G06F21/85 ,  G06F2009/45595 ,  H04L45/74

Abstract: A Network Interface Device (NID) of a web hosting server implements multiple virtual NIDs. A virtual NID is configured by configuration information in an appropriate one of a set of smaller blocks in a high-speed memory on the NID. There is a smaller block for each virtual NID. A virtual machine on the host can configure its virtual NID by writing configuration information into a larger block in PCIe address space. Circuitry on the NID detects that the PCIe write is into address space occupied by the larger blocks. If the write is into this space, then address translation circuitry converts the PCIe address into a smaller address that maps to the appropriate one of the smaller blocks associated with the virtual NID to be configured. If the PCIe write is detected not to be an access of a larger block, then the NID does not perform the address translation.

Abstract translation: 网络托管服务器的网络接口设备（NID）实现多个虚拟NID。 虚拟NID由NID中的高速存储器中的一组较小块中的适当的一个配置信息配置。 每个虚拟NID都有一个较小的块。 主机上的虚拟机可以通过将配置信息写入PCIe地址空间中的较大块来配置其虚拟NID。 NID上的电路检测到PCIe写入到较大块占用的地址空间中。 如果写入该空间，则地址转换电路将PCIe地址转换成较小的地址，该地址映射到与要配置的虚拟NID相关联的较小块中的适当的一个。 如果检测到PCIe写入不是较大块的访问，则NID不执行地址转换。

公开(公告)号：US09069602B2

公开(公告)日：2015-06-30

申请号：US14037214

申请日：2013-09-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/46 ,  G06F3/06

CPC classification number: G06F12/063 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F9/3004 ,  G06F9/3836 ,  G06F9/467 ,  G06F2212/251 ,  H04L45/74

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

Abstract translation: 事务存储器（TM）包括控制电路管线和相关联的存储器单元。 存储单元存储多个环。 对于每个环，流水线保持头指针和尾指针。 管道的环操作阶段将维护指针，因为值被放置在环上并被取消。 如果环未满，则put命令会使TM将值放入环中。 如果环不为空，则get命令使TM取环， 如果环具有至少预定量的可用缓冲空间，则具有低优先级命令的put将导致TM将值放入环中。 从一组ring命令获取，使TM从最高优先级非空环（指定的一组环）获取一个值。

公开(公告)号：US20150128119A1

公开(公告)日：2015-05-07

申请号：US14074632

申请日：2013-11-07

Applicant: Netronome Systems, Inc.

Inventor： Espen Skoglund ,  Rolf Neugebauer ,  Francois Henri Theron ,  Gavin J. Stark

IPC: G06F9/445

CPC classification number: G06F8/54 ,  G06F8/447

Abstract: A source code symbol can be declared to have a scope level indicative of a level in a hierarchy of scope levels, where the scope level indicates a circuit level or a sub-circuit level in the hierarchy. A novel instruction to the linker can define the symbol to be of a desired scope level. Location information indicates where different amounts of the object code are to be loaded into a system. A novel linker program uses the location information, along with the scope level information of the symbol, to uniquify instances of the symbol if necessary to resolve name collisions of symbols having the same scope. After the symbol uniquification step, the linker performs resource allocation. A resource instance is allocated to each symbol. The linker then replaces each instance of the symbol in the object code with the address of the allocated resource instance, thereby generating executable code.

Abstract translation: 源代码符号可以被声明为具有指示范围级别的层级中的级别的范围级别，其中范围级别指示层级中的电路级别或子电路级别。 对于链接器的新颖的指令可以将符号定义为期望的范围级别。 位置信息指示将不同量的目标代码加载到系统中的位置。 一个新的链接程序使用位置信息以及符号的范围级别信息来定义符号的实例，以解决具有相同范围的符号的名称冲突。 在符号唯一化步骤之后，链接器执行资源分配。 资源实例被分配给每个符号。 然后，链接器将目标代码中的符号的每个实例用分配的资源实例的地址替换，从而生成可执行代码。

公开(公告)号：US20150128117A1

公开(公告)日：2015-05-07

申请号：US14074606

申请日：2013-11-07

Applicant: Netronome Systems, Inc.

Inventor： Espen Skoglund ,  Rolf Neugebauer ,  Francois Henri Theron ,  Gavin J. Stark

IPC: G06F9/445

CPC classification number: G06F8/54

Abstract: A novel linker statically allocates resource instances of a non-memory resource at link time. In one example, a novel declare instruction in source code declares a pool of resource instances, where the resource instances are instances of the non-memory resource. A novel allocate instruction is then used to instruct the linker to allocate a resource instance from the pool to be associated with a symbol. Thereafter the symbol is usable in the source code to refer to an instance of the non-memory resource. At link time the linker allocates an instance of the non-memory resource to the symbol and then replaces each instance of the symbol with an address of the non-memory resource instance, thereby generating executable code. Examples of instances of non-memory resources include ring circuits and event filter circuits.

Abstract translation: 链接时，一个新的链接器静态分配非内存资源的资源实例。 在一个示例中，源代码中的一个新颖的声明指令声明资源实例池，其中资源实例是非内存资源的实例。 然后使用新的分配指令来指示链接器从池中分配与符号相关联的资源实例。 此后，该符号在源代码中可用于引用非存储器资源的实例。 在链接时，链接器会将非内存资源的实例分配给符号，然后用非内存资源实例的地址替换符号的每个实例，从而生成可执行代码。 非存储器资源的例子包括环形电路和事件滤波器电路。

公开(公告)号：US20150128113A1

公开(公告)日：2015-05-07

申请号：US14074640

申请日：2013-11-07

Applicant: Netronome Systems, Inc.

Inventor： Espen Skoglund ,  Rolf Neugebauer ,  Francois Henri Theron ,  Gavin J. Stark

IPC: G06F9/45 ,  G06F9/445

CPC classification number: G06F8/41 ,  G06F8/457 ,  G06F8/54

Abstract: A novel allocate instruction and a novel API call are received onto a compiler. The allocate instruction includes a symbol that identifies a non-memory resource instance. The API call is a call to perform an operation on a non-memory resource instance, where the particular instance is indicated by the symbol in the API call. The compiler replaces the API call with a set of API instructions. A linker then allocates a value to be associated with the symbol, where the allocated value is one of a plurality of values, and where each value corresponds to a respective one of the non-memory resource instances. After allocation, the linker generates an amount of executable code, where the API instructions in the code: 1) are for using the allocated value to generate an address of a register in the appropriate non-memory resource instance, and 2) are for accessing the register.

Abstract translation: 一个新的分配指令和一个新的API调用被接收到一个编译器上。 分配指令包括标识非内存资源实例的符号。 API调用是对非内存资源实例执行操作的调用，其中特定实例由API调用中的符号指示。 编译器使用一组API指令替换API调用。 链接器然后分配要与符号相关联的值，其中分配的值是多个值中的一个，并且其中每个值对应于非存储器资源实例中的相应一个。 分配后，链接器生成一定量的可执行代码，其中代码中的API指令：1）用于使用分配的值在适当的非内存资源实例中生成寄存器的地址，以及2）用于访问 登记册。