公开(公告)号：US09990307B1

公开(公告)日：2018-06-05

申请号：US14527642

申请日：2014-10-29

Applicant: Netronome Systems, Inc.

Inventor： Chirag P. Patel ,  Salma Mirza

IPC: G06F12/10 ,  G06F12/1081 ,  G06F13/30 ,  H04L12/40

CPC classification number: G06F12/1081 ,  G06F13/30 ,  H04L12/40071

Abstract: Packet information is stored in split fashion such that a first part is stored in a first device and a second part is stored in a second device. A split packet transmission DMA engine receives an egress packet descriptor. The descriptor does not indicate where the second part is stored but contains information about the first part. Using this information, the DMA engine causes a part of the first part to be transferred from the first device to the DMA engine. Address information in the first part indicates where the second part is stored. The DMA engine uses the address information to cause the second part to be transferred from the second device to the DMA engine. When both the part of the first part and the second part are stored in the DMA engine, then the entire packet is transferred in ordered fashion to an egress device.

公开(公告)号：US09413665B2

公开(公告)日：2016-08-09

申请号：US14464697

申请日：2014-08-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F9/26 ,  H04L12/801 ,  G06F12/10 ,  H04L12/935 ,  H04L12/861 ,  G06F13/16

CPC classification number: H04L47/10 ,  G06F12/1072 ,  G06F12/109 ,  G06F13/4234 ,  G06F2212/657 ,  H04L49/3072 ,  H04L49/9078

Abstract: Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing and handling the storing of packet portions into the memory, a packet engine is provided. A device interacting with the packet engine can use a PPI (Packet Portion Identifier) Addressing Mode (PAM) in communicating with the packet engine and in instructing the packet engine to store packet portions. Alternatively, the device can use a Linear Addressing Mode (LAM) to communicate with the packet engine. A PAM/LAM selection code field in a bus transaction value sent to the packet engine indicates whether PAM or LAM will be used.

Abstract translation: 在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。 管理和处理分组部分存储到存储器中的PDRSD不是提供分组引擎。 与分组引擎交互的设备可以使用PPI（分组部分标识符）寻址模式（PAM）与分组引擎进行通信，并指示分组引擎存储分组部分。 或者，设备可以使用线性寻址模式（LAM）与分组引擎进行通信。 发送到分组引擎的总线事务值中的PAM / LAM选择代码字段指示是否使用PAM或LAM。

公开(公告)号：US20160055112A1

公开(公告)日：2016-02-25

申请号：US14590920

申请日：2015-01-06

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/4221

Abstract: In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.

Abstract translation: 响应于从信用感知设备接收到一个新颖的“可返回PPI信用”命令，数据包引擎将为该设备维护的“信用回报”（CTBR）值发送回信用感知设备，并将零值 存储CTBR值。 信用感知设备将返回的信用额度添加到维护的“可用信用额”值。 信用感知设备使用“可用点数”值来确定是否可以发出PPI分配请求。 “可返回可用的PPI积分”命令不会导致任何PPI分配或解除分配。 在另一个新颖的方面，当信用感知设备的记录“可用可用”值为零或否定时，信用感知设备被允许向分组引擎发出一个PPI分配请求。 如果PPI分配请求不能被授权，则缓冲在分组引擎中，并在分组引擎内重新提交，直到分组引擎进行PPI分配。

公开(公告)号：US10146468B2

公开(公告)日：2018-12-04

申请号：US14492013

申请日：2014-09-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/28 ,  H04L12/00 ,  H04L29/08 ,  H04L12/64 ,  H04L29/06 ,  H04L12/863 ,  H04L12/861 ,  H04L12/935 ,  H04L12/801

Abstract: An addressless merge command includes an identifier of an item of data, and a reference value, but no address. A first part of the item is stored in a first place. A second part is stored in a second place. To move the first part so that the first and second parts are merged, the command is sent across a bus to a device. The device translates the identifier into a first address ADR1, and uses ADR1 to read the first part. Stored in or with the first part is a second address ADR2 indicating where the second part is stored. The device extracts ADR2, and uses ADR1 and ADR2 to issue bus commands. Each bus command causes a piece of the first part to be moved. When the entire first part has been moved, the device returns the reference value to indicate that the merge command has been completed.

公开(公告)号：US09804959B2

公开(公告)日：2017-10-31

申请号：US14530599

申请日：2014-10-31

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Steven W. Zagorianakos ,  Gavin J. Stark

IPC: G06F9/46 ,  G06F15/173 ,  G06F12/02 ,  H04L29/06

CPC classification number: G06F12/023 ,  G06F12/0223 ,  G06F2212/174 ,  G06F2212/254 ,  H04L69/22

Abstract: A method for supporting in-flight packet processing is provided. Packet processing devices (microengines) can send a request for packet processing to a packet engine before a packet comes in. The request offers a twofold benefit. First, the microengines add themselves to a work queue to request for processing. Once the packet becomes available, the header portion is automatically provided to the corresponding microengine for packet processing. Only one bus transaction is involved in order for the microengines to start packet processing. Second, the microengines can process packets before the entire packet is written into the memory. This is especially useful for large sized packets because the packets do not have to be written into the memory completely when processed by the microengines.

公开(公告)号：US09665519B2

公开(公告)日：2017-05-30

申请号：US14591003

申请日：2015-01-07

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/4221

Abstract: In response to receiving a “Return Available PPI Credits” command from a credit-aware (CA) device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the CA device, and zeroes out its stored CTBR value. The CA device adds the credits returned to a “Credits Available” value it maintains. The CA device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another aspect, the CA device issues one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.

公开(公告)号：US20160085477A1

公开(公告)日：2016-03-24

申请号：US14492013

申请日：2014-09-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark

IPC: G06F3/06 ,  G06F13/28 ,  G06F12/02

CPC classification number: G06F3/0647 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0683 ,  G06F13/28 ,  H04L12/00 ,  H04L12/6418 ,  H04L29/08 ,  H04L47/35 ,  H04L47/624 ,  H04L49/3072 ,  H04L49/9042 ,  H04L69/22

Abstract: An addressless merge command includes an identifier of an item of data, and a reference value, but no address. A first part of the item is stored in a first place. A second part is stored in a second place. To move the first part so that the first and second parts are merged, the command is sent across a bus to a device. The device translates the identifier into a first address ADR1, and uses ADR1 to read the first part. Stored in or with the first part is a second address ADR2 indicating where the second part is stored. The device extracts ADR2, and uses ADR1 and ADR2 to issue bus commands. Each bus command causes a piece of the first part to be moved. When the entire first part has been moved, then device returns the reference value to indicate that the merge command has been completed.

Abstract translation: 无地址合并命令包括数据项的标识符和参考值，但没有地址。 项目的第一部分存储在第一个位置。 第二部分存储在第二部分。 要移动第一部分以使第一部分和第二部分合并，命令通过总线发送到设备。 设备将标识符转换为第一地址ADR1，并使用ADR1读取第一部分。 存储在第一部分中或与第一部分一起存储是指示第二部分被存储在哪里的第二地址ADR2。 该设备提取ADR2，并使用ADR1和ADR2发出总线命令。 每个总线命令使第一部分的一部分被移动。 当整个第一部分被移动时，设备返回参考值以指示合并命令已经完成。

公开(公告)号：US20160057081A1

公开(公告)日：2016-02-25

申请号：US14464700

申请日：2014-08-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Ronald N. Fortino

IPC: H04L12/935 ,  H04L12/863 ,  H04L12/947

CPC classification number: H04L49/3018 ,  H04L47/624 ,  H04L49/252

Abstract: Within a networking device, packet portions from multiple PDRSDs (Packet Data Receiving and Splitting Devices) are loaded into a single memory, so that the packet portions can later be processed by a processing device. Rather than the PDRSDs managing the storing of packet portions into the memory, a packet engine is provided. The PDRSDs use a PPI addressing mode in communicating with the packet engine and in instructing the packet engine to store packet portions. A PDRSD requests a PPI from the packet engine, and is allocated a PPI by the packet engine, and then tags the packet portion to be written with the PPI and sends the packet portion and the PPI to the packet engine. Once the packet portion has been processed, a PPI de-allocation command causes the packet engine to de-allocate the PPI so that the PPI is available for allocating in association with another packet portion.

Abstract translation: 在网络设备内，来自多个PDRSD（分组数据接收和分离设备）的分组部分被加载到单个存储器中，使得分组部分稍后可以由处理设备处理。 不是将PDRSD管理分组部分存储到存储器中，而是提供分组引擎。 PDRSD使用PPI寻址模式与分组引擎进行通信，并指示分组引擎存储分组部分。 PDRSD从分组引擎请求PPI，并由分组引擎分配PPI，然后用PPI标记要写入的分组部分，并将分组部分和PPI发送到分组引擎。 一旦分组部分被处理，PPI解除分配命令使分组引擎去分配PPI，使得PPI可用于与另一分组部分相关联地分配。

公开(公告)号：US09703739B2

公开(公告)日：2017-07-11

申请号：US14590920

申请日：2015-01-06

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/4221

Abstract: In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.

公开(公告)号：US20160085701A1

公开(公告)日：2016-03-24

申请号：US14492015

申请日：2014-09-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F12/1081 ,  G06F13/1642 ,  G06F13/4027

Abstract: A chained Command/Push/Pull (CPP) bus command is output by a first device and is sent from a CPP bus master interface across a set of command conductors of a CPP bus to a second device. The chained CPP command includes a reference value. The second device decodes the command, in response determines a plurality of CPP commands, and outputs the plurality of CPP commands onto the CPP bus. The second device detects when the plurality of CPP commands have been completed, and in response returns the reference value back to the CPP bus master interface of the first device via a set of data conductors of the CPP bus. The reference value indicates to the first device that an overall operation of the chained CPP command has been completed.

Abstract translation: 链路命令/推/拉（CPP）总线命令由第一设备输出，并且从CPP总线主接口跨CPP总线的一组命令导体发送到第二设备。 链接的CPP命令包含一个参考值。 第二装置解码命令，作为响应确定多个CPP命令，并将多个CPP命令输出到CPP总线上。 第二设备检测多个CPP命令何时已经完成，并且响应于参考值经由CPP总线的一组数据导体将参考值返回到第一设备的CPP总线主接口。 参考值向第一个设备指示链接的CPP命令的整体操作已经完成。