公开(公告)号：US20070288707A1

公开(公告)日：2007-12-13

申请号：US11422915

申请日：2006-06-08

申请人： Robert B. Tremaine

发明人： Robert B. Tremaine

IPC分类号： G06F13/00

CPC分类号： G06F13/1684 ,  G06F12/0804 ,  G06F12/0886 ,  G06F2212/1016

摘要： Systems and methods for providing data modification operations in memory subsystems. Systems include a plurality of memory devices, a memory controller, one or more memory busses connected to the memory controller and a memory hub device. The memory controller receives and responds to memory access requests including memory update requests from a processor. The memory controller also generates a memory update command in response to receiving a memory update request. The memory hub device includes a first port, a second port and a control unit. The first port is in communication with the memory controller via one or more of the memory busses for transferring data and control information between the memory hub device and the memory controller. The second port is in communication with one or more of the memory devices. The control unit decodes the memory update command from the data and control information and accesses the memory devices via the second port to perform the memory update command local to the memory hub devices as a logical read-modify-write sequence.

摘要翻译： 在内存子系统中提供数据修改操作的系统和方法。 系统包括多个存储器设备，存储器控制器，连接到存储器控制器的一个或多个存储器总线和存储器集线器设备。 存储器控制器接收并响应包括来自处理器的存储器更新请求的存储器访问请求。 存储器控制器还响应于接收到存储器更新请求而产生存储器更新命令。 存储器集线器设备包括第一端口，第二端口和控制单元。 第一端口通过一个或多个存储器总线与存储器控制器通信，用于在存储器集线器设备和存储器控制器之间传送数据和控制信息。 第二端口与一个或多个存储器件通信。 控制单元从数据和控制信息中解码存储器更新命令，并通过第二端口访问存储器件，以将存储器集线器设备本地的存储器更新命令作为逻辑读 - 修改 - 写序列执行。

公开(公告)号：US07277988B2

公开(公告)日：2007-10-02

申请号：US10977846

申请日：2004-10-29

申请人： Kevin C. Gower ,  Mark W. Kellogg ,  Warren E. Maule ,  Thomas B. Smith, III ,  Robert B. Tremaine

发明人： Kevin C. Gower ,  Mark W. Kellogg ,  Warren E. Maule ,  Thomas B. Smith, III ,  Robert B. Tremaine

IPC分类号： G06F12/00

CPC分类号： G06F13/1684 ,  G06F12/0802 ,  G06F2212/401

摘要： A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.

摘要翻译： 包括存储器控制器，一个或多个存储器模块，上游存储器总线和下游存储器总线的级联互连系统。 一个或多个存储器模块包括具有高速缓存数据的第一存储器模块。 存储器模块和存储器控制器通过分组化的多传输接口经由下游存储器总线和上游存储器总线互连。 第一存储器模块和存储器控制器经由上游存储器总线和下游存储器总线直接通信。

公开(公告)号：US07082514B2

公开(公告)日：2006-07-25

申请号：US10666814

申请日：2003-09-18

申请人： Ramakrishnan Rajamony ,  Hazim Shafi ,  Robert B. Tremaine

发明人： Ramakrishnan Rajamony ,  Hazim Shafi ,  Robert B. Tremaine

IPC分类号： G06F12/00

CPC分类号： G06F13/1631 ,  G06F12/0215

摘要： A method and memory controller for adaptive row management within a memory subsystem provides metrics for evaluating row access behavior and dynamically adjusting the row management policy of the memory subsystem in conformity with measured metrics to reduce the average latency of the memory subsystem. Counters provided within the memory controller track the number of consecutive row accesses and optionally the number of total accesses over a measurement interval. The number of counted consecutive row accesses can be used to control the closing of rows for subsequent accesses, reducing memory latency. The count may be validated using a second counter or storage for improved accuracy and alternatively the row close count may be set via program or logic control in conformity with a count of consecutive row hits in ratio with a total access count. The control of row closure may be performed by a mode selection between always closing a row (non-page mode) or always holding a row open (page mode) or by intelligently closing rows after a count interval (row hold count) determined from the consecutive row access measurements. The logic and counters may be incorporated within the memory controller or within the memory devices and the controller/memory devices may provide I/O ports or memory locations for reading the count values and/or setting a row management mode or row hold count.

摘要翻译： 用于存储器子系统内的自适应行管理的方法和存储器控制器提供用于评估行访问行为的度量，并且根据所测量的度量来动态调整存储器子系统的行管理策略，以减少存储器子系统的平均等待时间。 存储器控制器内提供的计数器跟踪连续行访问的次数，以及可选的测量间隔内总访问次数。 可以使用计数的连续行访问次数来控制后续访问的行关闭，从而减少内存延迟。 可以使用第二计数器或存储器来对计数进行验证，以提高精确度，或者可以通过程序或逻辑控制来设置行关闭计数，这与根据总接入计数的比率的连续行命中的计数一致。 行闭合的控制可以通过总是关闭行（非页面模式）或总是保持行打开（页面模式）之间的模式选择来执行，或者通过在从所述第一模式确定的计数间隔（行保持计数）之后智能地关闭行来执行 连续行访问测量。 逻辑和计数器可以并入存储器控制器内或存储器件内，并且控制器/存储器设备可以提供用于读取计数值的I / O端口或存储器位置和/或设置行管理模式或行保持计数。

公开(公告)号：US06901483B2

公开(公告)日：2005-05-31

申请号：US10279246

申请日：2002-10-24

申请人： John T. Robinson ,  Robert B. Tremaine ,  Michael E. Wazlowski

发明人： John T. Robinson ,  Robert B. Tremaine ,  Michael E. Wazlowski

IPC分类号： G06F12/00 ,  G06F12/12

CPC分类号： G06F12/126

摘要： A method for selecting a line to replace in an inclusive set-associative cache memory system which is based on a least recently used replacement policy but is enhanced to detect and give special treatment to the reloading of a line that has been recently cast out. A line which has been reloaded after having been recently cast out is assigned a special encoding which temporarily gives priority to the line in the cache so that it will not be selected for replacement in the usual least recently used replacement process. This method of line selection for replacement improves system performance by providing better hit rates in the cache hierarchy levels above, by ensuring that heavily used lines in the levels above are not aged out of the levels below due to lack of use.

摘要翻译： 一种用于在包含集合关联高速缓存存储器系统中选择要替代的方法，该系统基于最近最近使用的替换策略，但是被增强以检测并对最近被抛出的行的重新加载进行特殊处理。 在最近被淘汰之后重新加载的行被分配一个专门的编码，它暂时优先地将高速缓存中的行优先，以便在通常的最近最近使用的替换过程中不被选择进行替换。 这种替代选线方法通过在上述缓存层次结构中提供更好的命中率来提高系统性能，通过确保上述级别中的使用过多的线路由于缺乏使用而不会超出以下级别。