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1.发明授权公开(公告)号：US06901483B2
公开(公告)日：2005-05-31
申请号：US10279246
申请日：2002-10-24
CPC分类号： G06F12/126
摘要： A method for selecting a line to replace in an inclusive set-associative cache memory system which is based on a least recently used replacement policy but is enhanced to detect and give special treatment to the reloading of a line that has been recently cast out. A line which has been reloaded after having been recently cast out is assigned a special encoding which temporarily gives priority to the line in the cache so that it will not be selected for replacement in the usual least recently used replacement process. This method of line selection for replacement improves system performance by providing better hit rates in the cache hierarchy levels above, by ensuring that heavily used lines in the levels above are not aged out of the levels below due to lack of use.
摘要翻译： 一种用于在包含集合关联高速缓存存储器系统中选择要替代的方法，该系统基于最近最近使用的替换策略，但是被增强以检测并对最近被抛出的行的重新加载进行特殊处理。 在最近被淘汰之后重新加载的行被分配一个专门的编码，它暂时优先地将高速缓存中的行优先，以便在通常的最近最近使用的替换过程中不被选择进行替换。 这种替代选线方法通过在上述缓存层次结构中提供更好的命中率来提高系统性能，通过确保上述级别中的使用过多的线路由于缺乏使用而不会超出以下级别。
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公开(公告)号：US09798528B2
公开(公告)日：2017-10-24
申请号：US11531313
申请日：2006-09-13
申请人： Yaoqing Gao , Gheorghe C. Cascaval , Allan H. Kielstra , Robert B. Tremaine , Michael E. Wazlowski , Lixin Zhang
发明人： Yaoqing Gao , Gheorghe C. Cascaval , Allan H. Kielstra , Robert B. Tremaine , Michael E. Wazlowski , Lixin Zhang
IPC分类号： G06F9/45 , G06F12/0811 , G06F12/08 , G06F12/0862
CPC分类号： G06F8/4442 , G06F8/40 , G06F8/41 , G06F8/443 , G06F8/4441 , G06F12/08 , G06F12/0811 , G06F12/0862 , G06F2212/6028
摘要： A solution for cooperative data prefetching that enables software control of a memory-side data prefetch and/or a processor-side data prefetch is provided. In one embodiment, the invention provides a solution for generating an application, in which access to application data for the application is improved (e.g., optimized) in program code for the application. In particular, a push request, for performing a memory-side data prefetch of the application data, and a prefetch request, for performing a processor-side data prefetch, are added to the program code. The memory-side data prefetch results in the application data being copied from a first data store to a second data store that is faster than the first data store while the processor-side data prefetch results in the application data being copied from the second data store to a third data store that is faster than the second data store.
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3.发明申请SOFTWARE SOLUTION FOR COOPERATIVE MEMORY-SIDE AND PROCESSOR-SIDE DATA PREFETCHING 有权合作存储器和处理器数据预编译软件解决方案公开(公告)号：US20080127131A1
公开(公告)日：2008-05-29
申请号：US11531313
申请日：2006-09-13
申请人： Yaoqing Gao , Gheorghe C. Cascaval , Allan H. Kielstra , Robert B. Tremaine , Michael E. Wazlowski , Lixin Zhang
发明人： Yaoqing Gao , Gheorghe C. Cascaval , Allan H. Kielstra , Robert B. Tremaine , Michael E. Wazlowski , Lixin Zhang
CPC分类号： G06F8/4442 , G06F8/40 , G06F8/41 , G06F8/443 , G06F8/4441 , G06F12/08 , G06F12/0811 , G06F12/0862 , G06F2212/6028
摘要： A solution for cooperative data prefetching that enables software control of a memory-side data prefetch and/or a processor-side data prefetch is provided. In one embodiment, the invention provides a solution for generating an application, in which access to application data for the application is improved (e.g., optimized) in program code for the application. In particular, a push request, for performing a memory-side data prefetch of the application data, and a prefetch request, for performing a processor-side data prefetch, are added to the program code. The memory-side data prefetch results in the application data being copied from a first data store to a second data store that is faster than the first data store while the processor-side data prefetch results in the application data being copied from the second data store to a third data store that is faster than the second data store.
摘要翻译： 提供了一种用于协同数据预取的解决方案，其实现对存储器侧数据预取和/或处理器侧数据预取的软件控制。 在一个实施例中，本发明提供了一种用于生成应用的解决方案，其中在应用的程序代码中改进（例如，优化）应用程序的应用数据的访问。 特别地，用于执行应用数据的存储器侧数据预取的推送请求和用于执行处理器侧数据预取的预取请求被添加到程序代码。 存储器侧数据预取导致应用数据从第一数据存储器复制到比第一数据存储器更快的第二数据存储器，而处理器侧数据预取导致应用数据从第二数据存储器复制 到比第二数据存储更快的第三数据存储。
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公开(公告)号：US08806177B2
公开(公告)日：2014-08-12
申请号：US11482222
申请日：2006-07-07
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0862 , G06F2212/6028 , G06F2212/651 , G06F2212/654
摘要： A method and system for prefetching in computer system are provided. The method in one aspect includes using a prefetch engine to perform prefetch instructions and to translate unmapped data. Misses to address translations during the prefetch are handled and resolved. The method also includes storing the resolved translations in a respective cache translation table. A system for prefetching in one aspect includes a prefetch engine operable to receive instructions to prefetch data from the main memory. The prefetch engine is also operable to search cache address translation for prefetch data and perform address mapping translation, if the prefetch data is unmapped. The prefetch engine is further operable to prefetch the data and store the address mapping in one or more cache memory, if the data is unmapped.
摘要翻译： 提供了一种在计算机系统中预取的方法和系统。 该方法在一个方面包括使用预取引擎来执行预取指令并转换未映射的数据。 在预取期间解决翻译错误的处理和解决。 该方法还包括将分辨的翻译存储在相应的缓存转换表中。 用于在一个方面预取的系统包括预取引擎，其可操作以接收从主存储器预取数据的指令。 如果预取数据未被映射，则预取引擎还可用于搜索缓存地址转换以获取预取数据并执行地址映射转换。 如果数据未被映射，则预取引擎还可操作以预取数据并将地址映射存储在一个或多个高速缓冲存储器中。
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公开(公告)号：US08674856B2
公开(公告)日：2014-03-18
申请号：US13587669
申请日：2012-08-16
IPC分类号： H03M7/34
摘要： In response to receipt of an input string, an attempt is made to identify, in a template store, a closely matching template for use as a compression template. In response to identification of a closely matching template that can be used as a compression template, the input string is compressed into a compressed string by reference to a longest common subsequence compression template. Compressing the input string includes encoding, in a compressed string, an identifier of the compression template, encoding substrings of the input string not having commonality with the compression template of at least a predetermined length as literals, and encoding substrings of the input string having commonality with the compression template of at least the predetermined length as a jump distance without reference to a base location in the compression template. The compressed string is then output.
摘要翻译： 响应于输入字符串的接收，尝试在模板存储器中识别紧密匹配的模板以用作压缩模板。 响应于可以用作压缩模板的紧密匹配的模板的识别，通过参考最长的公共子序列压缩模板将输入字符串压缩成压缩字符串。 压缩输入字符串包括在压缩字符串中编码压缩模板的标识符，将与压缩模板具有至少预定长度的压缩模板不一致的输入字符串的子串编码为文字，以及编码具有共同性的输入字符串的子串 至少具有预定长度的压缩模板作为跳跃距离，而不参考压缩模板中的基本位置。 然后输出压缩字符串。
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公开(公告)号：US08513972B2
公开(公告)日：2013-08-20
申请号：US13352900
申请日：2012-01-18
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H03K19/17764
摘要： A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.
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公开(公告)号：US20120023300A1
公开(公告)日：2012-01-26
申请号：US12843718
申请日：2010-07-26
CPC分类号： G06F12/1009 , G06F11/3471 , G06F12/1475 , G06F2201/88
摘要： Memory page management in a tiered memory system including a system that includes at least one page table for storing a plurality of entries, each entry associated with a page of memory and each entry including an address of the page and a memory tier of the page. The system also includes a control program configured for allocating pages associated with the entries to a software module, the allocated pages from at least two different memory tiers. The system further includes an agent of the control program capable of operating independently of the control program, the agent configured for receiving an authorization key to the allocated pages, and for migrating the allocated pages between the different memory tiers responsive to the authorization key.
摘要翻译： 包括包括至少一个用于存储多个条目的页表的系统的系统中的存储器页面管理，每个条目与存储器页面相关联，每个条目包括页面的地址和页面的存储器层。 该系统还包括配置用于将与条目相关联的页面分配给软件模块的控制程序，来自至少两个不同存储器层的所分配的页面。 该系统还包括能够独立于控制程序操作的控制程序的代理，被配置为接收对所分配的页面的授权密钥的代理，以及响应于授权密钥在不同存储器层之间迁移分配的页面。
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8.发明申请Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller 审中-公开组合内存包括通过IO控制器访问的存储内存中的逻辑分区公开(公告)号：US20110161597A1
公开(公告)日：2011-06-30
申请号：US12649856
申请日：2009-12-30
CPC分类号： G06F12/0895
摘要： A computer system having a combined memory. A first logical partition of the combined memory is a main memory region in a storage memory. A second logical partition of the combined memory is a direct memory region in a main memory. A memory controller comprising a storage controller is configured to receive a memory access request including a real address from a processor, determine whether the real address is for the first logical partition or for the second logical partition. If the address is for the first logical partition the storage controller communicates with an IO controller in the storage memory to service the memory access request. If the address is for the direct memory region, the memory controller services the memory access request in a conventional manner.
摘要翻译： 具有组合存储器的计算机系统。 组合存储器的第一逻辑分区是存储存储器中的主存储器区域。 组合存储器的第二逻辑分区是主存储器中的直接存储器区域。 包括存储控制器的存储器控制器被配置为从处理器接收包括实际地址的存储器访问请求，确定实际地址是为第一逻辑分区还是用于第二逻辑分区。 如果地址是用于第一逻辑分区，则存储控制器与存储器中的IO控制器通信以服务存储器访问请求。 如果地址用于直接存储区域，则存储器控制器以常规方式服务存储器访问请求。
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公开(公告)号：US20110087834A1
公开(公告)日：2011-04-14
申请号：US12576028
申请日：2009-10-08
申请人： Robert B. Tremaine
发明人： Robert B. Tremaine
CPC分类号： G06F12/0638 , Y10S707/99931
摘要： A memory system and methods for memory manage are presented. The memory system includes a volatile memory electrically connected to a high-density memory; a memory controller that expects data to be written or read to or from the memory system at a bandwidth and a latency associated with the volatile memory; a directory within the volatile memory that associates a volatile memory address with data stored in the high-density memory; and redundant storage in the high-density memory that stores a copy of the association between the volatile memory address and the data stored in the high-density memory. The methods for memory management allow writing to and reading from the memory system using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).
摘要翻译： 介绍了一种存储器系统和存储器管理方法。 存储器系统包括电连接到高密度存储器的易失性存储器; 期望以与易失性存储器相关联的带宽和等待时间从存储器系统写入或读取数据的存储器控制器; 易失性存储器内的目录，其将易失性存储器地址与存储在高密度存储器中的数据相关联; 以及高密度存储器中的冗余存储器，其存储易失性存储器地址和存储在高密度存储器中的数据之间的关联的副本。 用于存储器管理的方法允许使用第一存储器读/写接口（例如DRAM接口等）从存储器系统进行写入和读取，尽管数据存储在不同存储器类型（例如FLASH等）的器件中， 。
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公开(公告)号：US20110075740A1
公开(公告)日：2011-03-31
申请号：US12568765
申请日：2009-09-29
IPC分类号： H04B3/00
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译： 一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。 控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。 传输幅度和数据的单端或差分传输是功率模式的例子。 控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。
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